30V, Nch synchronous buck NexFET MOSFET™, SON3x3 PowerBlock, 15A
Product details
Parameters
Features
- Half-Bridge Power Block
- Optimized for High-Duty Cycle
- Up to 24 Vin
- 94.7% System Efficiency at 8 A
- 1.5 W PLoss at 8 A
- Up to 15-A Operation
- High-Frequency Operation (up to 1.5 MHz)
- High-Density SON 3.3-mm × 3.3-mm Footprint
- Optimized for 5-V Gate Drive
- Low-Switching Losses
- Ultra-Low Inductance Package
- RoHS Compliant
- Halogen Free
- Lead-Free Terminal Plating
Description
The CSD87333Q3D NexFET™ power block is an optimized design for synchronous buck and boost applications offering high-current, high-efficiency, and high-frequency capability in a small 3.3-mm × 3.3-mm outline. Optimized for 5-V gate drive applications, this product offers a flexible solution in high-duty cycle applications when paired with an external controller or driver.
Technical documentation
= Top documentation for this product selected by TI
| Type | Title | Date | |
|---|---|---|---|
| * | Datasheet | CSD87333Q3D Synchronous Buck NexFET Power Block datasheet (Rev. A) | Jan. 23, 2017 |
| Technical articles | How to choose the right power MOSFET or power block package for your application | Oct. 29, 2019 | |
| Technical articles | Discrete FETs vs. power blocks - how to choose the right SOA for your design | Jun. 06, 2019 | |
| Technical articles | Understanding the benefits of “lead-free” power MOSFETs | Feb. 07, 2019 | |
| Application note | QFN and SON PCB Attachment (Rev. B) | Aug. 24, 2018 | |
| Technical articles | When to use load switches in place of discrete MOSFETs | Feb. 03, 2016 | |
| Application note | Ringing Reduction Techniques for NexFET High Performance MOSFETs | Nov. 16, 2011 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Design tools & simulation
SLPM168A.ZIP (3 KB) - PSpice Model
FETPWRCALC — This tool is designed to assist engineers in the selection of Texas Instruments’ discrete power MOSFET and Power Block devices for their synchronous buck design. Users can input the conditions for their power supply and compare various discrete and power block solutions by power loss, relative (...)
Features
- Vary power supply conditions and observe TI’s most efficient solutions for any set of input parameters
- Select from a pre-established list of TI controllers or enter your own custom IC
- Rank solutions by effective power loss and compare by relative 1k price, device package, and total PCB footprint
- (...)
SPLR001.ZIP (824 KB)
Reference designs
PMP20172 — The PMP20172 reference design provides up to 36W on two USB Type-C outputs. Input is a 17VDC bus. The two outputs implement port power management. If only one port is in use, it is allocated the full 36W. If both ports are in use, power is split into 18W on each port. (...)
Design files
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download PMP20172 BOM.pdf (70KB) -
download PMP20172 Assembly Drawing.pdf (116KB) -
download PMP20172 PCB.pdf (1763KB) -
download PMP20172 CAD Files.zip (685KB) -
download PMP20172 Gerber.zip (650KB)
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| (DPB) | 8 | View options |
Ordering & quality
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