SLPS430A August   2013  – August 2014 CSD95375Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
  7. 7 Electrical Characteristics
  8. 8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Powering CSD95375Q4M And Gate Drivers
    3. 9.3 Undervoltage Lockout Protection (UVLO)
    4. 9.4 PWM Pin
    5. 9.5 SKIP# Pin
      1. 9.5.1 Zero Crossing (ZX) Operation
    6. 9.6 Integrated Boost-Switch
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Loss Curves
      2. 10.1.2 Safe Operating Curves (SOA)
      3. 10.1.3 Normalized Curves
      4. 10.1.4 Calculating Power Loss and SOA
        1. 10.1.4.1 Design Example
        2. 10.1.4.2 Calculating Power Loss
        3. 10.1.4.3 Calculating SOA Adjustments
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Recommended PCB Design Overview
      2. 11.1.2 Electrical Performance
      3. 11.1.3 Thermal Performance
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Recommended PCB Land Pattern
    3. 13.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLOSS
Power Loss(1) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 2.2 W
Power Loss(2) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 125°C		 2.6 W
VIN
VIN Quiescent Current, IQ PWM=Floating, VDD = 5 V, VIN= 14.5 V 1 µA
VDD
Standby Supply Current, IDD PWM = Float, SKIP# = VDD or 0 V 130 µA
SKIP# = Float 8 µA
Operating Supply Current, IDD PWM = 50% Duty cycle, ƒSW = 500 kHz 6.4 mA
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power-On Reset, VDD Rising 4.15 V
UVLO, VDD Falling 3.7 V
Hysteresis 0.2 mV
PWM and SKIP# I/O Specifications
Input Impedance, RI Pull Up to VDD 1700 kΩ
Pull Down (to GND) 800
Logic Level High, VIH 2.65 V
Logic Level Low, VIL 0.6
Hysteresis, VIH 0.2
Tri-State Voltage, VTS 1.3 2
Tri-state Activation Time (falling) PWM, tTHOLD(off1)(2) 60 ns
Tri-state Activation Time (rising) PWM, tTHOLD(off2)(2) 60
Tri-state Activation Time (falling) SKIP#, tTSKF(2) 1 µs
Tri-state Activation Time (rising) SKIP#, tTSKR(2) 1
Tri-state Exit Time PWM, t3RD(PWM)(2) 100 ns
Tri-state Exit Time SKIP#, t3RD(SKIP#)(2) 50 µs
BOOTSTRAP SWITCH
Forward Voltage, VFBST IF = 10 mA 120 240 mV
Reverse Leakage, IRLEAK VBST – VDD = 25 V 2 µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design