SLPS446D April   2014  – December 2016 CSD95379Q3M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Functional Description
        1. 7.2.1.1 Powering CSD95379Q3M and Gate Drivers
      2. 7.2.2 Undervoltage Lockout (UVLO) Protection
      3. 7.2.3 PWM Pin
      4. 7.2.4 SKIP# Pin
      5. 7.2.5 Zero Crossing (ZX) Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Loss Curves
      2. 8.1.2 Safe Operating Area (SOA) Curves
      3. 8.1.3 Normalized Curves
      4. 8.1.4 Calculating Power Loss and SOA
        1. 8.1.4.1 Design Example
        2. 8.1.4.2 Calculating Power Loss
        3. 8.1.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Electrical Performance
      2. 9.1.2 Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Drawing
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DNS|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

TA = 25°C (unless otherwise noted)
MIN MAX UNIT
VIN to PGND –0.3 20 V
VSW to PGND , VIN to VSW –0.3 20 V
VSW to PGND, VIN to VSW (<10 ns) –7 23 V
VDD to PGND –0.3 6 V
PWM, SKIP# to PGND –0.3 6 V
BOOT to PGND –0.3 25 V
BOOT to PGND (<10 ns) –2 28 V
BOOT to BOOT_R –0.3 6 V
PD Power dissipation 6 W
TJ Operating temperature –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
VDD Gate drive voltage 4.5 5.5 V
VIN Input supply voltage(1) 16 V
IOUT Continuous output current VIN = 12 V, VDD = 5 V, VOUT = 1.8 V,
ƒSW = 500 kHz, LOUT = 0.29 µH(2)		 20 A
IOUT-PK Peak output current(3) 45 A
ƒSW Switching frequency CBST = 0.1 µF (min) 25 2000 kHz
On time duty cycle 85%
Minimum PWM on time 40 ns
Operating temperature –40 125 °C
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(3) System conditions as defined in Note 1. Peak output current is applied for tp = 10 ms, duty cycle ≤1%.

6.4 Thermal Information

TA = 25°C (unless otherwise noted)
THERMAL METRIC MIN TYP MAX UNIT
RθJC(top) Junction-to-case thermal resistance (top of package)(1) 22.8 °C/W
RθJB Junction-to-board thermal resistance(2) 2.5
(1) RθJC(top) is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (.071-mm) thick Cu pad on a 1.5-in × 1.5-in,
0.06-in (1.52-mm) thick FR4 board.
(2) RθJB value based on hottest board temperature within 1 mm of the package.

6.5 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLOSS
Power loss(1) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 1.8 W
Power loss(2) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 125°C		 2.3 W
VIN
IQ VIN quiescent current PWM = float, VIN = 14.5 V, VDD = 5 V 1 µA
VDD
IDD Standby supply current PWM = float, VSKIP# = VDD or 0 V 130 µA
VSKIP# = float 8
IDD Operating supply current PWM = 50% duty cycle, ƒSW = 500 kHz 5.5 mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
VDD rising Power-on reset 4.15 V
VDD falling UVLO 3.7 V
Hysteresis 0.2 mV
PWM AND SKIP# I/O SPECIFICATIONS
RI Input impedance Pullup to VDD 1700 kΩ
Pulldown to GND 800
VIH Logic level high 2.65 V
VIL Logic level low 0.6 V
VIH Hysteresis 0.2 V
VTS Tri-state voltage 1.3 2 V
tHOLD(off1) Tri-state activation time (falling) PWM(2) 60 ns
tHOLD(off2) Tri-state activation time (rising) PWM(2) 60 ns
tTSKF Tri-state activation time (falling) SKIP#(2) 1 ns
tTSKR Tri-state activation time (rising) SKIP#(2) 1 ns
t3RD(PWM) Tri-state exit time PWM(2) 100 ns
t3RD(SKIP#) Tri-state exit time SKIP#(2) 50 us
BOOTSTRAP SWITCH
VFBOOT Forward voltage Measured from VDD to VBOOT, IF = 20 mA 120 240 mV
IRBOOT Reverse leakage(1) VBOOT – VDD = 25 V 2 µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design.

6.6 Typical Characteristics

TJ = 125°C, unless stated otherwise. The Typical CSD95379Q3M system characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness. See the Application and Implementation section for detailed explanation.
CSD95379Q3M graph01_SLPS446.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 1. Power Loss vs Output Current
CSD95379Q3M graph03p3_SLPS446.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 3. Safe Operating Area (SOA) – PCB Horizontal Mount
CSD95379Q3M graph06P2_SLPS446.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
LOUT = 0.29 µH IOUT = 18 A
Figure 5. Normalized Power Loss vs Frequency
CSD95379Q3M graph08_SLPS446.gif
VIN = 12 V VDD = 5 V ƒSW = 500 kHz
LOUT = 0.29 µH IOUT = 18 A
Figure 7. Normalized Power Loss vs Output Voltage
CSD95379Q3M graph10p2_SLPS446.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
LOUT = 0.29 µH IOUT = 18 A
Figure 9. Driver Current vs Frequency
CSD95379Q3M graph02_SLPS446.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 2. Power Loss vs Temperature
CSD95379Q3M graph05_SLPS446.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 4. Typical SOA
CSD95379Q3M graph07p2_SLPS446.gif
VDD = 5 V VOUT = 1.8 V LOUT = 0.29 µH
ƒSW = 500 kHz IOUT = 18 A
Figure 6. Normalized Power Loss vs Input Voltage
CSD95379Q3M graph09_SLPS446.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz IOUT = 18 A
Figure 8. Normalized Power Loss vs Output Inductance