SLPS382D January   2013  – August 2016 CSD97374Q4M

 

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Powering CSD97374Q4M and Gate Drivers
    3. 7.3 Undervoltage Lockout Protection (UVLO)
    4. 7.4 PWM Pin
    5. 7.5 SKIP# Pin
      1. 7.5.1 Zero Crossing (ZX) Operation
    6. 7.6 Integrated Boost-Switch
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Loss Curves
    3. 8.3 Safe Operating Curves (SOA)
    4. 8.4 Normalized Curves
    5. 8.5 Calculating Power Loss and SOA
      1. 8.5.1 Design Example
      2. 8.5.2 Calculating Power Loss
      3. 8.5.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
      3. 9.1.3 Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Recommended PCB Land Pattern
    2. 11.2 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1)
MIN MAX UNIT
VIN to PGND –0.3 30 V
VSW to PGND, VIN to VSW –0.3 30 V
VSW to PGND, VIN to VSW (< 10 ns) –7 33 V
VDD to PGND –0.3 6 V
PWM, SKIP# to PGND –0.3 6 V
BOOT to PGND –0.3 35 V
BOOT to PGND (< 10 ns) –2 38 V
BOOT to BOOT_R –0.3 6 V
BOOT to BOOT_R (duty cycle < 0.2 %) 8 V
PD Power dissipation 8 W
TJ Operating temperature –40 150 °C
TSTG Storage temperature –55 150 °C
(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
VDD Gate drive voltage 4.5 5.5 V
VIN Input supply voltage 24 V
IOUT Continuous output current VIN = 12 V, VDD = 5 V, VOUT = 1.8 V,
ƒSW = 500 kHz, LOUT = 0.29 µH(1)		 25 A
IOUT-PK Peak output current(2) 60 A
ƒSW Switching frequency CBST = 0.1 µF (min) 2000 kHz
On-time duty cycle 85 %
Minimum PWM on-time 40 ns
Operating temperature –40 125 °C
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) System conditions as defined in Note 1. Peak output current is applied for tp = 10 ms, duty cycle ≤ 1%.

6.4 Thermal Information

TA = 25°C (unless otherwise noted)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Thermal resistance, junction-to-case (top of package)(1) 22.8 °C/W
RθJB Thermal resistance, junction-to-board(2) 2.5 °C/W
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in, 0.06-in (1.52-mm) thick FR4 board.
(2) RθJB value based on hottest board temperature within 1 mm of the package.

6.5 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS
Power loss(1) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 2.3 W
Power loss(2) VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 2.5 W
Power loss(2) VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 125°C		 2.8 W
VIN
IQ VIN quiescent current PWM = floating, VDD = 5 V, VIN= 24 V 1 µA
VDD
IDD Standby supply current PWM = float, SKIP# = VDD or 0 V 130 µA
SKIP# = float 8
IDD Operating supply current PWM = 50% duty cycle, ƒSW = 500 kHz 8.2 mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
VDD rising Power-on reset 4.15 V
VDD falling UVLO 3.7 V
Hysteresis 0.2 mV
PWM AND SKIP# I/O SPECIFICATIONS
RI Input impedance Pullup to VDD 1700 kΩ
Pulldown (to GND) 800
VIH Logic level high 2.65 V
VIL Logic level low 0.6 V
VIH Hysteresis 0.2 V
VTS Tri-state voltage 1.3 2 V
tTHOLD(off1) Tri-state activation time (falling) PWM 60 ns
tTHOLD(off2) Tri-state activation time (rising) PWM 60 ns
tTSKF Tri-state activation time (falling) SKIP# 1 µs
tTSKR Tri-state activation time (rising) SKIP# 1 µs
t3RD(PWM)(2) Tri-state exit time PWM 100 ns
t3RD(SKIP#)(2) Tri-state exit time SKIP# 50 µs
BOOTSTRAP SWITCH
VFBST Forward voltage IF = 10 mA 120 240 mV
IRLEAK(2) Reverse leakage VBST – VDD = 25 V 2 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design.

6.6 Typical Characteristics

TJ = 125°C, unless stated otherwise.
CSD97374Q4M D001_SLPS382.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 1. Power Loss vs Output Current
CSD97374Q4M D003_SLPS382.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 3. Safe Operating Area – PCB Horizontal Mount The Typical CSD97374Q4M system characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W) x 3.5 in (L) x 0.062 in (T) and 6 copper layers of 1-oz copper thickness. See the
The Typical CSD97374Q4M system characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W) x 3.5 in (L) x 0.062 in (T) and 6 copper layers of 1-oz copper thickness. See theApplication and Implementation section for detailed explanation.
CSD97374Q4M D002_SLPS382.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 2. Power Loss vs Temperature
CSD97374Q4M D004_SLPS382.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 4. Typical Safe Operating Area (1)
CSD97374Q4M D005_SLPS382.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
IOUT = 25 A LOUT = 0.29 µH
Figure 5. Normalized Power Loss vs Frequency
CSD97374Q4M D007_SLPS382.gif
VIN = 12 V VDD = 5 V ƒSW = 500 kHz
IOUT = 25 A LOUT = 0.29 µH
Figure 7. Normalized Power Loss vs Output Voltage
CSD97374Q4M D009_SLPS382.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
IOUT = 25 A LOUT = 0.29 µH
Figure 9. Driver Current vs Frequency
CSD97374Q4M D006_SLPS382.gif
ƒSW = 500 kHz VDD = 5 V VOUT = 1.8 V
IOUT = 25 A LOUT = 0.29 µH
Figure 6. Normalized Power Loss vs Input Voltage
CSD97374Q4M D008_SLPS382.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz IOUT = 25 A
Figure 8. Normalized Power Loss vs Output Inductance
CSD97374Q4M D010_SLPS382.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
IOUT = 25 A LOUT = 0.29 µH
Figure 10. Driver Current vs Temperature