SLPS382D January   2013  – August 2016 CSD97374Q4M

 

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Powering CSD97374Q4M and Gate Drivers
    3. 7.3 Undervoltage Lockout Protection (UVLO)
    4. 7.4 PWM Pin
    5. 7.5 SKIP# Pin
      1. 7.5.1 Zero Crossing (ZX) Operation
    6. 7.6 Integrated Boost-Switch
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Loss Curves
    3. 8.3 Safe Operating Curves (SOA)
    4. 8.4 Normalized Curves
    5. 8.5 Calculating Power Loss and SOA
      1. 8.5.1 Design Example
      2. 8.5.2 Calculating Power Loss
      3. 8.5.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
      3. 9.1.3 Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Recommended PCB Land Pattern
    2. 11.2 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from C Revision (July 2013) to D Revision

Changes from B Revision (May 2013) to C Revision

  • Added dimension row b2 to the MECHANICAL DATA tableGo

Changes from A Revision (March 2013) to B Revision

  • Changed the Mechanical Drawing imageGo
  • Changed the Recommended PCB Land Pattern imageGo
  • Changed the Recommended Stencil Opening imageGo

Changes from * Revision (January 2013) to A Revision

  • Changed the ROC table, From: VSW to PGND, VIN to VSW (<20ns) MIN = -5 To: VSW to PGND, VIN to VSW (<10ns) MIN = -7Go
  • Changed the ROC table, From: BOOT to PGND (<20ns) MIN = -3 To: BOOT to PGND (<10ns) MIN = -2Go
  • Changed Logic Level High, VIH From: MAX = 2.6 To: MIN = 2.65Go
  • Changed Logic Level Low, VIL From: MIN = 0.6 To: MAX = 0.6Go
  • Changed Tri-State Voltage, VTS From: MIN = 1.2 To: MIN = 1.3Go