SLASEL0B October   2019  – June 2020 DAC11001A , DAC81001 , DAC91001


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Functional Block Diagram
      2.      High-Precision, Control-Loop Circuit
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1      Absolute Maximum Ratings
    2. 7.2      ESD Ratings
    3. 7.3      Recommended Operating Conditions
    4. 7.4      Thermal Information Package
    5. 7.5      Electrical Characteristics
    6. Table 1. Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. Table 2. Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. Table 3. Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. Table 4. Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 7.6      Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter Architecture
      2. 8.3.2 External Reference
      3. 8.3.3 Output Buffers
      4. 8.3.4 Internal Power-On Reset (POR)
      5. 8.3.5 Temperature Drift and Calibration
      6. 8.3.6 DAC Output Deglitch Circuit
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fast-Settling Mode and THD
      2. 8.4.2 DAC Update Rate Mode
    5. 8.5 Programming
      1. 8.5.1 Daisy-Chain Operation
      2. 8.5.2 CLR Pin Functionality and Software Clear
      3. 8.5.3 Output Update (Synchronous and Asynchronous)
        1. Synchronous Update
        2. Asynchronous Update
      4. 8.5.4 Software Reset Mode
    6. 8.6 Register Map
      1. 8.6.1 NOP Register (address = 00h) [reset = 0x000000h]
        1. Table 9. NOP Register Field Descriptions
      2. 8.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h]
        1. Table 10. DAC-DATA Register Field Descriptions
      3. 8.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
        1. Table 11. CONFIG1 Register Field Descriptions
      4. 8.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
        1. Table 12. DAC-CLEAR-DATA Register Field Descriptions
      5. 8.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
        1. Table 13. TRIGGER Register Field Descriptions
      6. 8.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
        1. Table 14. STATUS Register Field Descriptions
      7. 8.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
        1. Table 15. CONFIG2 Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Source Measure Unit (SMU)
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 9.2.2 Battery Test Equipment (BTE)
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 9.2.3 High-Precision Control Loop
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 9.2.4 Arbitrary Waveform Generation (AWG)
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Interfacing to a Processor
      2. 9.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 9.3.3 Embedded Resistor Configurations
        1. Minimizing Bias Current Mismatch
        2. 2x Gain configuration
        3. Generating Negative Reference
    4. 9.4 What to Do and What Not to Do
      1. 9.4.1 What to Do
      2. 9.4.2 What Not to Do
    5. 9.5 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Recommendations

To get the best performance out of the DACx1001, the power supply, grounding, and decoupling are very important. Use a PCB with a ground-plane reference, which helps in confining the digital return currents. A low mutual inductance path is created just beneath the high-frequency digital traces causing the return currents to follow the respective signal traces, thus minimizing crosstalk. On the other hand, dc signals spread over the ground plane without being confined below the signal trace. Therefore, in precision dc applications, limiting the common-impedance coupling is very difficult unless the ground planes are physically separated. Figure 72 shows a method to divide the grounds so that there is no common-mode current flow between the grounds, while maintaining the same dc potential across all grounds. This circuit assumes that the REFGND and LOAD-GND are provided from isolated power sources, therefore, there is no common-mode current flow through the reference or the load.

DAC11001A DAC91001 DAC81001 dac11001-power-and-signal-grounding.gifFigure 72. Power and Signal Grounding

When the load circuit is powered from a source referenced to AGND, and the LOAD-GND is shorted to AGND at the far end, the AGND-OUT must no longer be shorted to AGND locally near the DAC. The local shorting creates a ground loop, otherwise. The resulting connection that avoids the ground loop is shown in Figure 73.

DAC11001A DAC91001 DAC81001 dac11001-grounding-when-agnd-as-load-gnd.gifFigure 73. Grounding Scheme When AGND is Load Ground

When the reference source is powered from a power source with AGND as the ground, there is a possibility of common-impedance coupling causing a code-dependent shift in the reference voltage. To avoid undesired coupling, drive REFGND using a buffer that maintains the reference ground potential equals to that of AGND-OUT, as shown in Figure 74.

DAC11001A DAC91001 DAC81001 dac11001-refgnd-connection.gifFigure 74. Connecting the Reference Ground

Channel-to-channel dc crosstalk is a major concern in multichannel applications, such as battery test equipment. While the DACx1001 is single-channel, the crosstalk problem can appear at a system level when using multiple DACx1001 devices. The problem becomes severe when the grounds of the loads are shorted together creating a possible ground loop. In such cases, avoid the local short between AGND and AGND-OUT. Use a single short between AGND and DGND for all the DACs. If the PCB layout allows for the digital signal and analog power supplies to be kept separate, DGND and AGND can be combined to a single ground plane. Figure 75 shows an example circuit for minimizing dc crosstalk across DAC channels in a system.

DAC11001A DAC91001 DAC81001 dac11001-dc-crosstalk-reduction.gifFigure 75. Minimizing Multichannel DC Crosstalk

Power-supply bypassing and decoupling is key to keeping power supply noise, switching transients, and common-mode currents away from the DAC output. There are three main objective of power-supply bypassing:

  • Filtering: Filter out noise and ripple from power supplies
  • Bypassing: Supply switching or load transient currents locally by avoiding trace inductances
  • Decoupling: Stop local transient currents from impacting other circuits

To achieve these objectives, use the following 3-element scheme. Place a decoupling capacitor close to every power supply pin to provide the local current path for load and circuit switching transients. This capacitor must be referenced to the respective load ground for best load transient suppression. Use a 0.1-µF to 1-µF, X7R, multilayer ceramic capacitor (MLCC) for this purpose. For analog power supplies, a 10-Ω series resistor provides the best decoupling. For filtering the power-supply noise and ripple, 10-µF capacitors work best when placed at the power entry point of the board. An example decoupling scheme is shown in Figure 76.

DAC11001A DAC91001 DAC81001 dac11001-power-supply-decoupling.gifFigure 76. Power-Supply Decoupling