SLAS959D August 2013 – February 2018 DAC3151 , DAC3161 , DAC3171
PRODUCTION DATA.
In the SIF interface, there are three types of registers:
NORMAL: | The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL: | |||
AUTOSYNC: | A NORMAL register that causes a sync to be generated after the write is finished. These registers are most commonly used for settings such as offset and phase, where there is a word or block setup that extends across multiple registers, and all of the registers must be programmed before any take effect on the circuit. Therefore, the design allows all the registers to be written. When the last register for this block is finished, an autosync is generated telling the mixer to grab all the new SIF values. The autosync occurs on a mixer clock cycle so that there are no metastability errors. | |||
No RESET Value: | These are NORMAL registers, but for one reason or another reset value cannot be specified. The reason may be because the register has some read_only bits or some internal logic partially controls the bit values. An example is the SIF_CONFIG6 register, where the bits come from the temperature sensor and the fuses. Depending on which fuses are blown and the temperature of the die, the reset value will be different. | |||
FUSE controlled: | While not a type of register, FUSE_controlled may be seen in the default-value column for the register. Fuses will change the default value, and the value shown in the default-value column is for when no fuses are blown. | |||
READ_ONLY: | Registers that are internal wires ANDed with the address bus, and then connected to the SIF output data bus. | |||
WRITE_TO_CLEAR: | These registers are just like NORMAL registers with one exception. These registers can be written and read; however, when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is written to 0. In this way, interrupts are captured and stay constant until cleared by the user. |
Name | Address | Default | Bit 15 (MSB) | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 (LSB) |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
config0 | 0x00 | 0x44FC | qmc _offset _ena |
dual_ena | chipwidth (1:0) | rev | twos | sif4_ena | reserved | fifo_ena | alarm_out_ena | alarm_out_pol | alignrx _ena |
lvdssyncrx _ena |
lvdsdataclk _ena |
reserved | synconly _ena |
|
config1 | 0x01 | 0x600E | iotest_ena | reserved | fullword _interface _ena |
64cnt _ena |
dacclkgone _ena |
dataclkgone _end | collision _ena |
reserved | daca _compliment |
reserved | sif_sync | sif_ sync_ena | alarm_ 2away _ena |
alarm _1away _ena |
alarm _collision _ena |
reserved |
config2 | 0x02 | 0x3FFF | reserved | reserved | lvdsdata_ena (13:0) | |||||||||||||
config3 | 0x03 | 0x0000 | datadlya (2:0) | clkdlya (2:0) | datadlyb(2:0) | clkdlyb(2:0) | extref _ena | reserved | dual_ena | |||||||||
config4 | 0x04 | 0x0000 | reserved | iotest_results (13:0) | ||||||||||||||
config5 | 0x05 | 0x0000 | alarm _from _zerochka |
reserved | alarms_from_fifoa (2:0) | reserved | alarm _dacclk _gone |
alarm _dataclk _ gone |
clock _gone |
alarm _from _ iotesta |
reserved | reserved | ||||||
config6 | 0x06 | 0x0000 | tempdata (7:0) | fuse_cntl (5:0) | reserved | |||||||||||||
config7 | 0x07 | 0xFFFF | alarms_mask (15:0) | |||||||||||||||
config8 | 0x08 | 0x6000 | reserved | qmc_offseta (12:0) | ||||||||||||||
config9 | 0x09 | 0x8000 | fifo_offset (2:0) | reserved | ||||||||||||||
config10 | 0x0A | 0xF080 | coarse_dac (3:0) | fuse_ sleep | reserved | reserved | tsense _sleep |
clkrecv _ena |
sleepa | sleepb | reserved | reserved | ||||||
config11 | 0x0B | 0x1111 | reserved | reserved | reserved | reservedspares_west (3:0) | ||||||||||||
config12 | 0x0C | 0x3A7A | reserved | iotest_pattern0 (13:0) | ||||||||||||||
config13 | 0x0D | 0x36B6 | reserved | iotest_pattern1 (13:0) | ||||||||||||||
config14 | 0x0E | 0x2AEA | reserved | iotest_pattern2 (13:0) | ||||||||||||||
config15 | 0x0F | 0x0545 | reserved | iotest_pattern3 (13:0) | ||||||||||||||
config16 | 0x10 | 0x0585 | reserved | iotest_pattern4 (13:0) | ||||||||||||||
config17 | 0x11 | 0x0949 | reserved | iotest_pattern5 (13:0) | ||||||||||||||
config18 | 0x12 | 0x1515 | reserved | iotest_pattern6 (13:0) | ||||||||||||||
config19 | 0x13 | 0x3ABA | reserved | iotest_pattern7 (13:0) | ||||||||||||||
config20 | 0x14 | 0x0000 | sifdac _ena |
reserved | sifdac (13:0) | |||||||||||||
config21 | 0x15 | 0xFFFF | sleepcntl (15:0) | |||||||||||||||
config22 | 0x16 | 0x0000 | fa002_data(15:0) | |||||||||||||||
config23 | 0x17 | 0x0000 | fa002_data(31:16) | |||||||||||||||
config24 | 0x18 | 0x0000 | fa002_data(47:32) | |||||||||||||||
config25 | 0x19 | 0x0000 | fa002_data(63:48) | |||||||||||||||
config127 | 0x7F | 0x0044 | reserved | reserved | reserved | reserved | reserved | titest_voh | titest_vol | vendorid (1:0) | versionid (2:0) |