The serial port of the DAC31x1 is a flexible serial interface that communicates with industry-standard microprocessors and microcontrollers. The interface provides read and write access to all registers used to define the operating modes of DAC31x1. The interface is compatible with most synchronous transfer formats, and can be configured as a 3 or 4 pin interface by sif4_ena in register XYZ. In both configurations, SCLK is the serial interface input clock, and SDENB is serial interface enable. For 3-pin configuration, SDIO is a bidirectional pin for both data in and data out. For 4-pin configuration, SDIO is data in only, and SDO is data out only. Data are input into the device with the rising edge of SCLK. Data are output from the device on the falling edge of SCLK.
Each read and write operation is framed by the serial data enable bar signal (SDENB) asserted low. The first frame byte is the instruction cycle, which identifies the following data transfer cycle as read or write, as well as the 7-bit address to be accessed. Table 1 indicates the function of each bit in the instruction cycle, and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.
|Bit||7 (MSB)||6||5||4||3||2||1||0 (LSB)|
|Description||Read or Write||A6||A5||A4||A3||A2||A1||A0|
|Read or Write||Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC31x1 and a low indicates a write operation to DAC31x1.|
|[A6:A0]||Identifies the address of the register to be accessed during the read or write operation.|
Figure 70 shows the serial interface timing diagram for a DAC31x1 write operation. SCLK is the serial interface clock input to DAC31x1. Serial data enable SDENB is an active low input to DAC31x1. SDIO is serial data in. Input data to DAC31x1 is clocked on the rising edges of SCLK.
Figure 71 illustrates the serial interface timing diagram for a DAC31x1 read operation. SCLK is the serial interface clock input to DAC31x1. Serial data enable SDENB is an active low input to DAC31x1. SDIO is serial data in during the instruction cycle. In 3-pin configuration, SDIO is data out from the DAC31x1 during the data transfer cycle, while SDO is in a high-impedance state. In 4-pin configuration, both SDIO and SDO are data out from the DAC31x1 during the data transfer cycle. At the end of the data transfer, SDIO and SDO output low on the final falling edge of SCLK until the rising edge of SDENB when SDIO and SDO go to a high-impedance state.