SLASF07 September   2023 DAC43901-Q1 , DAC43902-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Comparator Mode
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast-Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
        1. 7.3.2.1 Voltage Reference and DAC Transfer Function
        2. 7.3.2.2 Power-Supply as Reference
        3. 7.3.2.3 Internal Reference
        4. 7.3.2.4 External Reference
      3. 7.3.3 Programming Interface
      4. 7.3.4 Nonvolatile Memory (NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.4.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.4.1.2 NVM-CRC-FAIL-INT Bit
      5. 7.3.5 Power-On Reset (POR)
      6. 7.3.6 External Reset
      7. 7.3.7 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
      2. 7.4.2 PWM Fade-In Fade-Out Mode
      3. 7.4.3 Sequential Turn-Indicator Animation Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Sequential Turn Indicator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Logarithmic Fade-In Fade-Out
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Sequential Turn-Indicator Animation Mode

The DAC43901-Q1 and DAC43902-Q1 support state-machines preconfigured for sequential turn-indicator animation, as shown in Figure 7-7, Figure 7-8, and Figure 7-9. The fade-in is done logarithmically. Table 7-9 shows the pin multiplexing of the PWM channels and the programming interface. The PWM outputs are available on the digital pins in the standalone mode. The device goes into standalone mode when the VREF/MODE pin is pulled high. In this mode, the programming interface is disabled. The device functions per the configurations in the NVM. The digital programming interface (I2C and SPI) pins are open-drain outputs and must be pulled up to function as PWM outputs. Pulling the VREF/MODE pin low brings the device into programming mode. When the PWM output mode is enabled, all four programming interface pins act as PWM outputs, even if not used. Partial selection is not possible. The PWM duty-cycle resolution is 7 bits. The animation pattern is triggered by an external signal applied to the TRIG-IN pin or by controlling the power supply to the smart DAC. When more than four channels are required, multiple devices can be cascaded by daisy-chaining the TRIG-OUT (DAC43902-Q1 only) and the TRIG-IN pins, as shown in Figure 7-8. In some cases, the LED modules are in separate subsystems and there is no way to daisy-chain the device; the only common connection is the power. Figure 7-9 shows a configuration wherein the delay for the first channel in the following devices is configured to match the cumulative delay of all the channels in the predecessor devices. The timing diagram of the sequential turn-indicator animation is shown in Figure 7-10. The fade-in timing configurations are done as described in Section 7.4.2. The PWM frequency is configured as per Table 7-7.

Table 7-9 Animation Pin Mapping
ANIMATION INTERFACE MULTIPLEXED PROGRAMMING PIN PIN NUMBER
PWM0 SDA/SCLK 8
PWM1 A0/SDI 7
PWM2 (DAC43902-Q1 only) SCL/SYNC 6
PWM3 (DAC43902-Q1 only) NC/SDO 5
TRIG-IN TRIG-IN 1
TRIG-OUT (DAC43902-Q1 only) TRIG-OUT 11
GUID-20210407-CA0I-DBSH-HVXN-L1MH58SLC36B-low.svg Figure 7-7 Sequential Turn-Indicator Animation
GUID-20210620-CA0I-7MNS-XMJF-H99L5RCVH6GS-low.svg Figure 7-8 Sequential Turn-Indicator Animation With Cascaded Devices
GUID-20210506-CA0I-MJKX-2LH1-XW4JFX8FK3M8-low.svg Figure 7-9 Sequential Turn-Indicator Animation Using Unconnected LED Modules
GUID-20210506-CA0I-NW9W-MDWS-VGVPQLTL94Z3-low.svg Figure 7-10 Sequential Turn-Indicator Animation Timing Diagram

Each PWM channel can be started after a delay with respect to the previous respective channel. Figure 7-10 shows that there is a separate delay for the first channel, PWM0, and then a common delay for other channels, including the TRIG-OUT pin. Equation 6 gives the SLEW-RATE calculation for DAC43902-Q1. Equation 5 gives the calculation for total fade-in time. The channel delays are a function of the SLEW-RATE, as given in Equation 4 and the delay settings, CH0-DELAY or COM-DELAY. Equation 7 is used to calculate the delay. CH0-DELAY defines the delay before starting the fade-in operation for PWM0, and COM-DELAY defines the delay before starting the fade-in for all other PWM channels, including the delay before toggling TRIG-OUT. The delay applies even when the fade-in is disabled by writing 0 for FADE-IN-RATE. In this case, a predefined delay setting of 256 is considered. The DAC43902-Q1 does not have the fade-out function.

Equation 6. t S L E W ( μ s ) = 2.4 × S L E W _ R A T E + 5.6

where:

  • tSLEW_RATE is the fade-in unit time in microseconds/step.
  • SLEW_RATE is the FADE-IN-RATE as specified in Table 7-10 for DAC43902-Q1.

Equation 7. t D E L A Y = D E L A Y × t S L E W

where:

  • tDELAY is the delay before the fade-in operation for each channel in seconds.
  • DELAY is the CH0-DELAY or COM-DELAY as specified in Table 7-10 for DAC43902-Q1 or as specified in Table 7-10 for DAC43901-Q1.
  • tSLEW is the unit slew rate calculated as per Equation 4.

Table 7-10 Fade-In Configuration
PARAMETER LOCATION ADDRESS [BITS] DEFAULT VALUE DESCRIPTION
PWM-MAX SRAM, NVM 0x21 [15:9] 0xF7 Maximum PWM duty cycle.
PWM-MIN SRAM, NVM 0x20 [15:9] 0x00 Minimum PWM duty cycle.
FADE-IN-RATE SRAM, NVM 0x23 [15:0] 0x0000 See Equation 4, Equation 6, and Equation 5.
CH0-DELAY SRAM, NVM 0x24 [15:0] 0x0000 Delay for PWM0.
COM-DELAY SRAM, NVM 0x25 [15:0] 0x0000 Delay for all channels and TRIGGER-OUT except PWM0.
PWM-FREQ SRAM, NVM 0x22 [11:7] 0x00 Frequency selection as per Table 7-7.

Table 7-11 shows the list of register settings done for the device configuration.

Table 7-11 DAC43902-Q1 Register Settings
REGISTER NAME ADDRESS DEFAULT VALUE
COMMON-CONFIG 0x1F 0x13F9
DAC-0-VOUT-CMP-CONFIG 0x15 0x0407
DAC-1-VOUT-CMP-CONFIG 0x03 0x0400
STATE-MACHINE-CONFIG0 0x27 0x0003