SLASF07 September   2023 DAC43901-Q1 , DAC43902-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Comparator Mode
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast-Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
        1. 7.3.2.1 Voltage Reference and DAC Transfer Function
        2. 7.3.2.2 Power-Supply as Reference
        3. 7.3.2.3 Internal Reference
        4. 7.3.2.4 External Reference
      3. 7.3.3 Programming Interface
      4. 7.3.4 Nonvolatile Memory (NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.4.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.4.1.2 NVM-CRC-FAIL-INT Bit
      5. 7.3.5 Power-On Reset (POR)
      6. 7.3.6 External Reset
      7. 7.3.7 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
      2. 7.4.2 PWM Fade-In Fade-Out Mode
      3. 7.4.3 Sequential Turn-Indicator Animation Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Sequential Turn Indicator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Logarithmic Fade-In Fade-Out
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics: General

all minimum/maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V, reference tied to VDD, gain = 1 ×, DAC output pin (TRIG-OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL REFERENCE
Initial accuracy TA = 25°C for all measurements 1.1979 1.212 1.224 V
Reference output temperature coefficient(1) (2) 60 ppm/°C 
EXTERNAL REFERENCE (VREF)
External reference input voltage 1.7 VDD V
VREF input impedance(1) (3) 192 kΩ-ch
EEPROM
Endurance(1) –40°C ≤ TA ≤ +85°C  20000 Cycles
TA = 125°C  1000
Data retention(1) 50 Years
EEPROM programming write cycle time(1) 200 ms
Device boot-up time(1) Time taken from power valid (VDD ≥ 1.7 V) to output valid state (output state as programmed in EEPROM), 0.5-µF capacitor on the CAP pin 5 ms
DIGITAL INPUTS
Pin capacitance Per pin 10 pF
POWER
IDD Current flowing into VDD Sleep mode, internal reference disabled, external reference at 5.5 V 28 µA
Sleep mode, internal reference enabled, additional current through internal reference(1) 10
DAC channels enabled, internal reference enabled, additional current through internal reference per DAC channel(1) 12.5 µA-ch
Normal operation, state machine enabled(1) DAC43901-Q1 1.02 mA
DAC43902-Q1 1.2
(1) Specified by design and characterization, not production tested.
(2) Measured at –40°C and +125°C and calculated the slope.
(3) Impedances for the DAC channels are connected in parallel.