SLASF07 September   2023 DAC43901-Q1 , DAC43902-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Comparator Mode
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast-Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
        1. 7.3.2.1 Voltage Reference and DAC Transfer Function
        2. 7.3.2.2 Power-Supply as Reference
        3. 7.3.2.3 Internal Reference
        4. 7.3.2.4 External Reference
      3. 7.3.3 Programming Interface
      4. 7.3.4 Nonvolatile Memory (NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.4.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.4.1.2 NVM-CRC-FAIL-INT Bit
      5. 7.3.5 Power-On Reset (POR)
      6. 7.3.6 External Reset
      7. 7.3.7 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
      2. 7.4.2 PWM Fade-In Fade-Out Mode
      3. 7.4.3 Sequential Turn-Indicator Animation Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Sequential Turn Indicator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Logarithmic Fade-In Fade-Out
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.2 Detailed Design Procedure

The TL431LI-Q1 adjustable, precision shunt regulator can be used to supply the DAC43901-Q1 from the 12-V system voltage. The TL431LI-Q1 has a 2.5-V precision reference. Two 10-kΩ resistors are used, as shown in the simplified figure, to regulate the output voltage to 5 V to supply DAC43901-Q1.

The state machine in DAC43901-Q1 is enabled by default; therefore, the PWM outputs are used with the preset parameters when the VREF/MODE pin is pulled high. To change these default parameters, pull the VREF/MODE pin low to enter programming mode, and write a 0 to the SM-START and SM-EN bits of the STATE-MACHINE-CONFIG0 register to disable the state machine. After the state machine is disabled, program the following SRAM parameters and register settings:

On the rising edge of TRIG-IN, the DAC43901-Q1 PWM outputs fade-in to the 7-bit PWM duty cycle defined in the PWM-MAX parameter located in bits [6:0] of SRAM location 0x21. On the falling edge of TRIG-IN, the PWM outputs fade-out to the 7-bit PWM duty cycle defined in the PWM-MIN parameter located in bits [6:0] of SRAM location 0x20.

The 5-bit PWM frequency is set in the PWM-FREQ parameter located in bits [11:7] of SRAM location 0x22. The available PWM frequencies are given in Table 7-7. The TPS92633-Q1 LED driver used in the example schematic recommends a 200-Hz PWM frequency with a 1% to 100% duty cycle for brightness control. In that case, the maximum frequency setting of 31 can be set in PWM-FREQ to get a PWM output frequency of 218 Hz. Make sure to left-shift this value by 7 bits when loading the parameter into the SRAM location.

Both PWM output channels use the same fade-in rate and fade-out rate as defined in the FADE-IN SLEW-RATE and FADE-OUT SLEW-RATE parameters located in bits [15:0] of SRAM locations 0x23 and 0x26, respectively. The total fade-in or fade-out time can be calculated using Equation 4 and Equation 5. The SLEW-RATE parameter is used in Equation 4 to get the tSLEW_RATE in ms/step. For example, if a value of 2366 is used for the FADE-IN SLEW-RATE parameter, the resulting tSLEW-RATE is 5.68 ms/step.

The information given in Table 7-5 is used to calculate the total number of duty-cycle steps in the fade-in or fade-out transition. If PWM-MIN is set to 0 and PWM-MAX is set to 0x7F, a total of 176 steps are needed. Equation 5 is used to calculate the total fade time, tFADE as one second.

The delays between each channel are configured in the CH0-DELAY and COM-DELAY parameters in bits [15:0] of SRAM location 0x24 and 0x25, respectively. CH0-DELAY represents the delay between the rising edge of trigger and the start of channel 0. COM-DELAY represents the delay between the start of channel 0 and the start of channel 1. The delay time is calculated using Equation 7. If a delay value of 88 is set in the COM-DELAY parameter, the delay between the start of channel 0 and start of channel 1 is 500 ms.

After all register settings and SRAM parameters are configured, restart the state machine by writing ones to the SM-START and SM-EN bits of the STATE-MACHINE-CONFIG0 register. Save these settings to the NVM by writing a 1 to the NVM-PROG bit of the COMMON-TRIGGER register. Pull the VREF/MODE pin high to put DAC43901-Q1 in standalone mode and enable the PWM outputs on the digital interface pins.

The pseudocode for getting started with a logarithmic fade-in fade-out application is as follows:

//SYNTAX: WRITE <REGISTER NAME (REGISTER ADDRESS)>, <MSB DATA>, <LSB DATA>
//Pull VREF/MODE pin low to enter programming mode
//Disable the state machine
WRITE STATE-MACHINE-CONFIG0(0x27), 0x00, 0x00
//Power-up DAC channel 0, disable the internal reference
WRITE COMMON-CONFIG(0x1F), 0x03, 0xFF
//Enable comparator settings for channel 0, and set reference to VDD
WRITE DAC-0-VOUT-CMP-CONFIG(0x15), 0x04, 0x07
//Set the comparator threshold to mid-scale
WRITE SRAM-ADDR(0x2B), 0x00, 0x27
WRITE SRAM-DATA(0x2C), 0x80, 0x00
//Set max PWM duty cycle to 100%
WRITE SRAM-ADDR(0x2B), 0x00, 0x21
WRITE SRAM-DATA(0x2C), 0x00, 0x7F
//Set min PWM duty cycle to 0%
WRITE SRAM-ADDR(0x2B), 0x00, 0x20
WRITE SRAM-DATA(0x2C), 0x00, 0x00
//Set PWM frequency to 218Hz
WRITE SRAM-ADDR(0x2B), 0x00, 0x22
WRITE SRAM-DATA(0x2C), 0x0F, 0x80
//Set fade-in time to 1 s
WRITE SRAM-ADDR(0x2B), 0x00, 0x23
WRITE SRAM-DATA(0x2C), 0x09, 0x39
//Set fade-out time to 1 s
WRITE SRAM-ADDR(0x2B), 0x00, 0x26
WRITE SRAM-DATA(0x2C), 0x09, 0x3E
//Set the CH0 delay to 0
WRITE SRAM-ADDR(0x2B), 0x00, 0x24
WRITE SRAM-DATA(0x2C), 0x00, 0x00
//Set the COM delay to 500 ms
WRITE SRAM-ADDR(0x2B), 0x00, 0x25
WRITE SRAM-DATA(0x2C), 0x00, 0x58
//Enable and start the state machine
WRITE STATE-MACHINE-CONFIG0(0x27), 0x00, 0x03
//Save all settings in NVM
WRITE COMMON-TRIGGER(0x20) 0x00, 0x02
//Pull the VREF/MODE pin high to enter standalone mode