DLPS215A July   2021  – September 2022 DLP301S

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • FQS|99
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20210309-CA0I-9KRT-VWTM-RHH6WP8HXKDC-low.gif Figure 5-1 FQS Package99-Pin LGA(Bottom View)
Table 5-1 Pin Functions – Connector Pins(1)
PIN TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm)
NAME NO.
DATA INPUTS
D_N(0) C6 I SubLVDS Double Data, Negative 3.15
D_P(0) C5 I SubLVDS Double Data, Positive 3.09
D_N(1) D7 I SubLVDS Double Data, Negative 3.24
D_P(1) D6 I SubLVDS Double Data, Positive 3.29
D_N(2) D5 I SubLVDS Double Data, Negative 2.00
D_P(2) D4 I SubLVDS Double Data, Positive 1.97
D_N(3) F7 I SubLVDS Double Data, Negative 3.96
D_P(3) F6 I SubLVDS Double Data, Positive 4.04
D_N(4) F5 I SubLVDS Double Data, Negative 1.39
D_P(4) F4 I SubLVDS Double Data, Positive 1.39
D_N(5) G6 I SubLVDS Double Data, Negative 2.85
D_P(5) G5 I SubLVDS Double Data, Positive 2.90
D_N(6) H5 I SubLVDS Double Data, Negative 2.37
D_P(6) H4 I SubLVDS Double Data, Positive 2.37
D_N(7) H7 I SubLVDS Double Data, Negative 3.22
D_P(7) H6 I SubLVDS Double Data, Positive 3.26
DCLK_N E6 I SubLVDS Double Clock, Negative 2.33
DCLK_P E5 I SubLVDS Double Clock, Positive 2.33
CONTROL INPUTS
LS_WDATA B3 I LPSDR(1) Single Write data for low speed interface. 17.1
LS_CLK B5 I LPSDR Single Clock for low-speed interface 15.28
DMD_DEN_ARSTZ B2 I LPSDR Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 17.91
LS_RDATA B7 O LPSDR Single Read data for low-speed interface 12.29
POWER(3)
VBIAS A6 Power Supply voltage for positive bias level at micromirrors
VBIAS A22 Power
VOFFSET B21 Power Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes.
Supply voltage for offset level at micromirrors.
VOFFSET G2 Power
VRESET A5 Power Supply voltage for negative reset level at micromirrors.
VRESET A23 Power
VDD C2 Power
VDD A19 Power
VDD A20 Power
VDD A21 Power Supply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs.
Supply voltage for normal high level at micromirror address electrodes.
VDD B20 Power
VDD C2 Power
VDD D2 Power
VDD D3 Power
VDD D23 Power
VDD E2 Power
VDD F2 Power
VDD F3 Power
VDD F23 Power
VDDI B6 Power Supply voltage for SubLVDS receivers.
VDDI B19 Power
VDDI C3 Power
VDDI C23 Power
VDDI E3 Power
VDDI E23 Power
VDDI G3 Power
VDDI G23 Power
VSS A2 Ground Common return. Ground for all power
VSS A3 Ground
VSS A4 Ground
VSS A7 Ground
VSS A24 Ground
VSS B22 Ground
VSS B23 Ground
VSS B24 Ground
VSS C4 Ground
VSS C7 Ground
VSS C19 Ground
VSS C22 Ground
VSS E4 Ground
VSS E7 Ground
VSS E19 Ground Common return. Ground for all power
VSS E22 Ground
VSS G4 Ground
VSS G7 Ground
VSS G19 Ground
VSS G22 Ground
VSS G24 Ground
VSS H2 Ground
VSS H3 Ground
VSS H23 Ground
VSS H24 Ground
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQS ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
Table 5-2 Pin Functions – No Connect
NUMBER SYSTEM BOARD
TEST PADS
A1 Do not connect.
A17 Do not connect.
A18 Do not connect.
B8 Do not connect.
B17 Do not connect.
B18 Do not connect.
C8 Do not connect.
UNUSED PINS
B4 Do not connect.
C20 Do not connect.
C21 Do not connect.
D19 Do not connect.
D20 Do not connect.
D21 Do not connect.
D22 Do not connect.
E20 Do not connect.
E21 Do not connect.
F19 Do not connect.
F20 Do not connect.
F21 Do not connect.
F22 Do not connect.
G20 Do not connect.
G21 Do not connect.
H19 Do not connect.
H20 Do not connect.
H21 Do not connect.
H22 Do not connect.