DLPS229A December   2022  – February 2024 DLP4621-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
      1. 5.4.1 Illumination Overfill Diagram
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
      1.      Electrical and Timing Diagrams
    8. 5.8  Switching Characteristics
      1. 5.8.1 LPSDR and Test Load Circuit Diagrams
    9. 5.9  System Mounting Interface Loads
      1.      System Interface Loads Diagram
    10. 5.10 Micromirror Array Physical Characteristics
      1. 5.10.1 Micromirror Array Physical Characteristics Diagram
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 DMD Voltage Supplies
      4. 6.3.4 Asynchronous Reset
      5. 6.3.5 Temperature Sensing Diode
        1. 6.3.5.1 Temperature Sense Diode Theory
    4. 6.4 System Optical Considerations
      1. 6.4.1 Numerical Aperture and Stray Light Control
      2. 6.4.2 Pupil Match
      3. 6.4.3 Illumination Overfill
    5. 6.5 DMD Image Performance Specification
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Power-Up Procedure
      2. 7.3.2 Power Supply Power-Down Procedure
      3. 7.3.3 Power Supply Sequencing Requirements
    4. 7.4 Layout Guidelines
    5. 7.5 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Third-Party Products Disclaimer
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 DMD Handling
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FQX|120
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MIN MAX UNIT
SUPPLY VOLTAGE
VDD Supply voltage for LVCMOS core logic(1)
Supply voltage for LPSDR low speed interface		 –0.5 2.3 V
VDDI Supply voltage for SubLVDS receivers(1) –0.5 2.3 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(1)(2) –0.5 8.75 V
VBIAS Supply voltage for micromirror electrode(1) –0.5 17 V
VRESET Supply voltage for micromirror electrode(1) –11 0.5 V
|VDDI – VDD| Supply voltage delta (absolute value)(3) 0.3 V
|VBIAS –VOFFSET| Supply voltage delta (absolute value)(4) 8.75 V
|VBIAS – VRESET| Supply voltage delta (absolute value)(5) 28 V
INPUT VOLTAGE
Input voltage for LVCMOS Inputs(1) –0.5 VDD + 0.5 V
Input voltage for other inputs SubLVDS(1)(6) –0.5 VDDI + 0.5 V
INPUT PINS
|VID| SubLVDS input differential voltage (absolute value)(6) 810 mV
|IID| SubLVDS input differential current 10 mA
CLOCK FREQUENCY
Fmax_LS Clock frequency for low speed interface LS_CLK 100 130 MHz
TEMPERATURE DIODE
ITEMP_DIODE Max current source into temperature diode 120 µA
ENVIRONMENTAL
TARRAY Operating DMD array temperature –40 105 °C
(1) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw and permanent damage to the device.
(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw and permanent damage to the device.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw and permanent damage to the device.
(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. SubLVDS differential inputs must not exceed the specified limit or damage to the internal termination resistors may result.