7.3.1 DMD Regulators

DLPA1000 contains three switch-mode power supplies that power the DMD. These rails are VOFS, VBIAS, and VRST. 100 ms after pulling the PROJ_ON pin high, VOFS is powered up, followed by VBIAS and VRST with an additional 10-ms delay. Only after all three rails are enabled can the LED driver and STROBE DECODER circuit be enabled. If any one of the rails encounters a fault such as an output short, all three rails are disabled simultaneously. The detailed power-up and power-down diagram is shown in Figure 3.

Power-up or down is initiated by pulling the PROJ_ON pin high or low, respectively. Upon pulling PROJ_ON high, the device enters ACTIVE2 mode immediately because DMD_EN and VLED_EN bits default to 1.

Figure 3. Power-Up and Power-Down Timing of the DMD REGULATOR and VLED Supplies

7.3.2 RGB Strobe Decoder

DLPA1000 contains RGB color-sequential circuitry that is composed of six NMOS switches, the LED driver, the strobe decoder and the LED current control. The NMOS switches are connected to the terminals of the external LED package and turn the currents through the LEDs on and off. The strobe decoder controls the gates of the NMOS switches according to the LED_SEL[1:0] input signals and the MAP bit of the SYSTEM register. The MAP bit selects one of two package configurations. A ‘1’ indicates a cathode-cathode-anode package and a ‘0’ indicates the common anode package. The two package connections are shown in Figure 4 and the corresponding switch map in Table 1 and Table 2.

The LED_SEL[1:0] signals typically receive a rotating code switching from RED to GREEN to BLUE and then back to RED. When the LED_SEL[1:0] input signals select a specific color, the NMOSFETs are controlled based on the color selected, and a 10-bit current control DAC for this color is selected that provides a color correction current to the RGB LEDs feedback control network.

Figure 4. LEFT: Switch Connection for a Common-Anode LED Assembly
RIGHT: Switch Connection for a Cathode-Cathode-Anode LED Assembly

The switching of the six NMOS switches is controlled such that switches are returned to the OPEN position first before the CLOSED connections are made (Break Before Make). The dead time between opening and closing switches is controlled through the BBM register. Switches that already are in the CLOSED position and are to remain in the CLOSED state according to the SWCNTRL register, are not opened during the BBM delay time.

7.3.3 LED Current Control

DLPA1000 provides time-sequential circuitry to drive three LEDs with independent current control. A system based on a common anode LED configuration is shown in Figure 6 and consists of a buck-boost converter which provides the voltage to drive the LEDs, three switches connected to the cathodes of the LEDs, a 100-mΩ resistor used to sense the LED current, and a current DAC to control the LED current.

The STROBE DECODER controls the switch positions as described in the section above. With all switches in the OPEN position, the buck-boost output assumes an output voltage of 3.5 V.

For a common-anode RGB LED configuration (MAP = 0, default), the BUCK-BOOST output voltage (VLED) assumes a value such that the voltage drop across the sense resistor equals (SW4_IDAC[9:0] × 100 mΩ) when SW4 is closed. The exact value of VLED depends on the current setting and the voltage drop across the LED but is limited to 6.5 V. When the STROBE decoder switches from SW4 to SW5, the Buck-Boost assumes a new output voltage such that the sense voltage equals (SW5_IDAC[9:0] × 100 mΩ), and finally, when SW6 is selected, V_{(RLIM_K)} is regulated to (SW6_IDAC[9:0] × 100 mΩ).

Similarly, the regulation current setting switches from SW4_IDAC[9:0] to SW5_IDAC[9:0] to SW6_IDAC[9:0] depending on the LED_SEL[1:0] setting with a MAP setting of 1 (cathode-cathode-anode configuration). See Table 2 for details.

7.3.3.2 Transient Current Limiting

Typically the forward voltages of the GREEN and BLUE diodes are close to each other (~3 V to 4 V) but V_f of the RED diode is significantly lower (1.8 V to 2.5 V). This can lead to a current spike in the RED diode when the strobe controller switches from GREEN or BLUE to RED because VLED is regulated to a higher voltage than required to drive the RED diode. DLPA1000 provides transient current limiting for each switch to limit the current in the LEDs during the transition. The transient current limit value is controlled through the ILIM[2:0] bits in the IREG register. The same register also contains three bits to select which switch employs the transient current limiting feature. In a typical application it is required only for the RED diode and the ILIM[2:0] value should be set approximately 10% higher than the DC regulation current. The effect that the transient current limit has on the LED current is shown in Figure 5.

LEFT: RED LED current without transient current limit. The current overshoots because the buck-boost voltage starts at the (higher) level of the GREEN or BLUE LED.

RIGHT: LED current with transient current limit.

Figure 5. RED LED Current With and Without Transient Current Limit

Figure 6. Block Diagram of the LED Driver Circuitry

7.3.4 Measurement System

The measurement system is composed of a 8:1 analog multiplexer (MUX), a programmable-gain amplifier and a comparator. It works together with the DPP processor to provide:

• White-point correction (WPC) by independently adjusting the R/G/B LED currents, after measuring the brightness of each color from an external light sensor.
• A measurement of the battery voltage.
• A measurement of the LED forward voltage.
• A measurement of the exact LED current.
• A measurement of temperature as derived by measuring the voltage across an external thermistor.

A block diagram of the measurement system is shown in Figure 7.

Figure 7. Block Diagram of the Measurement System

7.3.5 Protection Circuits

DLPA1000 has several protection circuits to protect the IC as well as the system from damage due to excessive power consumption, die temperature, or over-voltages. These circuits are described below.

7.3.5.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)

DLPA1000 continuously monitors the junction temperature and issues a HOT interrupt if temperature exceeds the HOT threshold. If the temperature continues to increase above the thermal shutdown threshold, all rails are disabled and the TSD bit in the INT register is set. Once the temperature drops by 15°C, the output rails are powered up in sequence and normal operation resumes (DMD_EN bit is not reset by TSD fault).

Figure 8. Definition of the Thermal Shutdown and Hot-Die Temperature Warning

7.3.5.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)

If the battery voltage drops below the BAT_LOW threshold (typically 3 V) the BAT_LOW interrupt is issued but normal operation continues. Once the battery drops below the undervoltage threshold (typically 2.3 V) the UVLO interrupt is issued, all rails are powered down in sequence, the DMD_EN bit is reset, and the part enters STANDBY mode. The power rails cannot be re-enabled before the input voltage recovers to > 2.4 V. To re-enable the rails, the PROJ_ON pin must be toggled.

Figure 9. Undervoltage Lockout is Asserted When the Input Supply Drops Below the UVLO Threshold

7.3.6 Interrupt Pin (INTZ)

The interrupt pin is used to signal events and fault conditions to the host processor. Whenever a fault or event occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is pulled low. The INTZ pin is released (returns to HiZ state) and fault bits are cleared when the INT register is read by the host. However, if a failure persists, the corresponding INT bit remains set and the INTZ pin is pulled low again after a maximum of 32 µs.

Interrupt events include fault conditions such as power-good faults, over-voltage, over-temperature shut-down, and under-voltage lock-out.

The MASK register is used to mask events from generating interrupts, i.e. from pulling the INTZ pin low. The MASK settings affect the INTZ pin only and have no impact on protection and monitor circuits themselves. When an interrupt is masked, the event causing the interrupt still sets the corresponding bit in the INT register. However, it does not pull the INTZ pin low.

Note that persisting fault conditions such as thermal shutdown can cause the INTZ pin to be pulled low for an extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT register to see when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.

7.3.7 Serial Peripheral Interface (SPI)

DLPA1000 provides a 4-wire SPI port that supports high-speed serial data transfers up to 33.3 MHz. Register and data buffer write and read operations are supported. The SPI_CSZ input serves as the active low chip select for the SPI port. The SPI_CSZ input must be forced low in order to write or read registers and data buffers. When SPI_CSZ is forced high, the data at the SPI_DIN input is ignored, and the SPI_DOUT output is forced to a high-impedance state. The SPI_DIN input serves as the serial data input for the port; the SPI_DOUT output serves as the serial data output. The SPI_CLK input serves as the serial data clock for both the input and output data. Data is latched at the SPI_DIN input on the rising edge of SPI_CLK, while data is clocked out of the SPI_DOUT output on the falling edge of SPI_CLK. Figure 10 illustrates the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant bit is the write/not read bit. For the W/nR bit, a 1 indicates a write operation, while a 0 indicates a read operation. The remaining seven bits of the command byte are the register address targeted by the write or read operation. The SPI port supports write and read operations for multiple sequential register addresses through the implementation of an auto-increment mode. As shown in Figure 10, the auto-increment mode is invoked by simply holding the SPI_CSZ input low for multiple data bytes. The register address is automatically incremented after each data byte transferred, starting with the address specified by the command byte. After reaching address 0x7Fh the address pointer jumps back to 0x00h.

Figure 10. SPI Protocol

Table 4. Modes of Operation

7.5.1 Password Protected Registers

Register address 0x11h through 0x27h can be read-accessed the same way as any other register but are protected against accidental write operations through the PASSWORD register (address 0x10h). To write to a protected register, first:

• Write data 0xBAh to register address 0x10h, then
• Write data 0xBEh to register address 0x10h.

Both writes must be consecutive, i.e. there must be no other read or write operation in between sending the two bytes. Once the password has been successfully written, register 0x11h through 0x27h are unlocked and can be write accessed using the regular SPI protocol. They remain unlocked until any byte other than 0xBAh is written to the PASSWORD register or the part is power cycled.

To check if the registers are unlocked, read back the PASSWORD register. If the data returned is 0x00h, the registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.

Table 5. Register Address Map

7.6.1 Chip ID (CHIPID) Register (address = 0x00h) [reset = A6h]

7.6.2 Enable (ENABLE) Register (address = 0x01h) [reset = 3h]

7.6.3 Switch Transient Current Limit (IREG) Register (address = 0x02h) [reset = 28h]

7.6.4 SW4 LED DC Regulation Current, MSB (SW4MSB) Register (address = 0x03h) [reset = 0h]

7.6.5 SW4 LED DC Regulation Current, LSB (SW4LSB) Register (address = 0x04h) [reset = 0h]

7.6.6 SW5 LED DC Regulation Current, MSB (SW5MSB) Register (address = 0x05h) [reset = 0h]

7.6.7 SW5 LED DC Regulation Current, LSB (SW5LSB) Register (address = 0x06h) [reset = 0h]

7.6.8 SW6 LED DC Regulation Current, MSB (SW6MSB) Register (address = 0x07h) [reset = 0h]

7.6.9 SW6 LED DC Regulation Current, LSB (SW6LSB) Register (address = 0x08h) [reset = 0h]

7.6.10 Analog Front End Control (AFE) Register (address = 0x0Ah) [reset = 0h]

7.6.11 Strobe Decode - Break Before Make Timing Control (BBM) Register (address = 0x0Bh) [reset = 0h]

7.6.12 Interrupt (INT) Register (address = 0x0Ch) [reset = X]

7.6.13 Interrupt Mask (MASK) Register (address = 0x0Dh) [reset = 0h]

7.6.14 Password (PASSWORD) Register (address = 0x10h) [reset = 0h]

7.6.15 System Configuration (SYSTEM) Register (address = 0x11h) [reset = 0h]

7.6.16 EEPROM User Register, Byte0 (BYTE0) (address = 0x20h) [reset = 0h]

7.6.17 EEPROM User Register, Byte1 (BYTE1) (address = 0x21h) [reset = 0h]

7.6.18 EEPROM User Register, Byte2 (BYTE2) (address = 0x22h) [reset = 0h]

7.6.19 EEPROM User Register, Byte3 (BYTE3) (address = 0x23h) [reset = 0h]

7.6.20 EEPROM User Register, Byte4 (BYTE4) (address = 0x24h) [reset = 0h]

7.6.21 EEPROM User Register, Byte5 (BYTE5) (address = 0x25h) [reset = 0h]

7.6.22 EEPROM User Register, Byte6 (BYTE6) (address = 0x26h) [reset = 0h]

7.6.23 EEPROM User Register, Byte7 (BYTE7) (address = 0x27h) [reset = 0h]