DLPS052 October 2015 DLPA3000
The power-up and power-down sequence is important to ensure a correct operation of the DLPA3000 and to prevent damage to the DMD. The DLPA3000 controls the correct sequencing of the DMD_VRESET, DMD_VBIAS and DMD_VOFFSET to ensure a reliable operation of the DMD.
The general startup sequence of the supplies was described previously in Supply and Monitoring. The power-up sequence of the high-voltage DMD lines is especially important to prevent damaging the DMD. Damage could include, for example, that DMD mirrors get stuck or collide. A too-large delta voltage between DMD_VBIAS and DMD_VOFFSET could cause the damage and should therefore be prevented.
After PROJ_ON is pulled high, the DMD buck converters and LDOs are powered (PWR1-4) the DMD high voltage lines (HV) are sequentially enabled. First, DMD_VOFFSET is enabled. After a delay, VOFS_STATE_DURATION (register 0x10) DMD_VBIAS is enabled. Finally, after another delay, VBIAS_STATE_DURATION (register 0x11) DMD_VRESET is enabled. The DLPA3000 is now fully powered and ready for starting projection.
In normal power-down mode, the power down is initiated after pulling PROJ_ON pin low. 25 ms after PROJ_ON is pulled low, DMD_VBIAS and DMD_VRESET will stop regulating. 10 ms later, DMD_OFFSET will stop regulating. When DMD_OFFSET stops regulating, RESET_Z is pulled low. 1 ms after the DMD_OFFSET stops regulating, all three voltages are discharged. Finally, all other supplies are turned off. INT_Z remains high during the power-down sequence since no fault occurred. During power down, it is guaranteed that the HV levels do not violate the DMD specifications on these three lines. For this, it is important to select the capacitors such that CVOFFSET is equal to CVRESET and CVBIAS is ≤ CVOFFSET, CVBIAS.
The fast power-down mode (Figure 19) is started in case a fault occurs (INT_Z will be pulled low), for instance due to overheating. The fast power-down mode can be enabled or disabled through register 0x01, FAST_SHUTDOWN_EN. The mode is enabled by default. After the fault occurs, regulation of DMD_VBIAS and DMD_VRESET is stopped. The time (delay) between fault and stop of regulation can be controlled through register 0x0F (VBIAS/VRST_DELAY). The delay can be selected between 4 µs and ≈1.1 ms, where the default is ≈540 µs. A defined delay-time after the regulation stopped, all three high voltages lines are discharged and RESET_Z is pulled low. The delay can be controlled through register 0x0F (VOFS/VRESETZ_DELAY). Delay can be selected between 4 µs and ≈1.1ms. The default is ≈4 µs. Finally, the internal DMD_EN signal is pulled low.
Now the DLPA3000 is in a standby state. It remains in standby state until the fault resolves. In case the fault resolves, a restart is initiated. It starts then by powering up PWR_3 and follows the regular power up as depicted in Figure 19. Again, for proper discharge timing and levels, the capacitors should be selected such that CVOFFSET is equal to CVRESET and CVBIAS is ≤ CVOFFSET, CVBIAS.