DLPS052 October   2015 DLPA3000

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Parameters
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply and Monitoring
        1. 7.3.1.1 Supply
        2. 7.3.1.2 Monitoring
          1. 7.3.1.2.1 Block Faults
          2. 7.3.1.2.2 Low Battery and UVLO
          3. 7.3.1.2.3 Auto LED Turn Off Functionality
          4. 7.3.1.2.4 Thermal Protection
      2. 7.3.2 Illumination
        1. 7.3.2.1 Programmable Gain Block
        2. 7.3.2.2 LDO Illum
        3. 7.3.2.3 Illumination Driver A
        4. 7.3.2.4 RGB Strobe Decoder
          1. 7.3.2.4.1 Break Before Make (BBM)
          2. 7.3.2.4.2 Openloop Voltage
          3. 7.3.2.4.3 Transient Current Limit
        5. 7.3.2.5 Illumination Monitoring
          1. 7.3.2.5.1 Power Good
          2. 7.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 7.3.2.6 Load Current and Supply Voltage
        7. 7.3.2.7 Illumination Driver Plus Power FETS Efficiency
      3. 7.3.3 DMD Supplies
        1. 7.3.3.1 LDO DMD
        2. 7.3.3.2 DMD HV Regulator
          1. 7.3.3.2.1 Power-Up and Power-Down Timing
        3. 7.3.3.3 DMD/DLPC Buck Converters
        4. 7.3.3.4 DMD Monitoring
          1. 7.3.3.4.1 Power Good
          2. 7.3.3.4.2 Overvoltage Fault
      4. 7.3.4 Buck Converters
        1. 7.3.4.1 LDO Bucks
        2. 7.3.4.2 General Purpose Buck Converters
        3. 7.3.4.3 Buck Converter Monitoring
          1. 7.3.4.3.1 Power Good
          2. 7.3.4.3.2 Overvoltage Fault
        4. 7.3.4.4 Buck Converter Efficiency
      5. 7.3.5 Auxiliary LDOs
      6. 7.3.6 Measurement System
      7. 7.3.7 Digital Control
        1. 7.3.7.1 SPI
        2. 7.3.7.2 Interrupt
        3. 7.3.7.3 Fast-Shutdown in Case of Fault
        4. 7.3.7.4 Protected Registers
        5. 7.3.7.5 Writing to EEPROM
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Setup Using DLPA3000
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Typical Application with DLPA3000 Internal Block Diagram
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 SPI Connections
    4. 10.4 RLIM Routing
    5. 10.5 LED Connection
    6. 10.6 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

SPI

The DLPA3000 provides a 4-wire SPI port that supports two SPI clock frequency modes: 0 MHz to 36 MHz, and 20 MHz to 40MHz. The clock frequency mode can be set in register 0x17, DIG_SPI_FAST_SEL. The interface supports both read and write operations. The SPI_SS_Z input serves as the active low chip select for the SPI port. The SPI_SS_Z input must be forced low for writing to or reading from registers. When SPI_SS_Z is forced high, the data at the SPI_MOSI input is ignored, and the SPI_MISO output is forced to a high-impedance state. The SPI_MOSI input serves as the serial data input for the port; the SPI_MISO output serves as the serial data output. The SPI_CLK input serves as the serial data clock for both the input and output data. Data at the SPI_MOSI input is latched on the rising edge of SPI_CLK, while data is clocked out of the SPI_MISO output on the falling edge of SPI_CLK. Figure 25 illustrates the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant bit is the write/not-read bit. For the W/nR bit, a 1 indicates a write operation, while a 0 indicates a read operation. The remaining seven bits of the command byte are the register address targeted by the write or read operation. The SPI port supports write and read operations for multiple sequential register addresses through the implementation of an auto-increment mode. As shown in Figure 25, the auto-increment mode is invoked by simply holding the SPI_SS_Z input low for multiple data bytes. The register address is automatically incremented after each data byte transferred, starting with the address specified by the command byte. After reaching address 0x7Fh, the address pointer jumps back to 0x00h.

DLPA3000 SPI_Protocol.gifFigure 25. SPI Protocol