DLPS023C January 2012 – August 2015 DLPC300
Refer to the PDF data sheet for device specific package drawings
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DLPC300 controller enables integration of the DLP3000 WVGA chipset into small-form-factor and low-cost light steering applications. Example end equipments for the 0.3 WVGA chipset include 3D scanning or metrology systems with structured light, interactive displays, chemical analyzers, medical instruments, and other end equipments requiring spatial light modulation (or light steering and patterning).
The DLPC300 is one of the two devices in the DLP3000 WVGA chipset (see Figure 14). The other device is the DLP3000 DMD. For proper operation of the chipset, the DLPC300 requires a serial flash device with configuration information. This information is loaded after RESET is released. The configuration information is available for download from the DLPR300 product folder.
The DLP3000 WVGA chipset consists of two individual components:
Figure 14 illustrates the connectivity between the individual components in the chipset, which include the following internal chipset interfaces:
Figure 15 illustrates the connectivity between the chipset and other key system-level components, which include the following external chipset interfaces:
The DLP3000 WVGA Chipset supports a single 24-bit parallel RGB interface for data transfers from another device. The system input also requires that proper configuration of the PARK and RESETinputs to ensure reliable operation.
See Specifications for further details on each of the following interfaces.
The DLP3000 WVGA chipset supports I2C commands to control its operation. The control interface allows another master processor to send commands to the DLP3000 WVGA chipset to configure the chipset, query system status or perform real-time operations, such as set the LED drive current or display splash screens stored in serial flash memory. The DLPC300 offers two different slave addresses. The I2C_ADDR_SEL pin provides the ability to select an alternate set of 7-bit I2C slave address. If I2C_ADDR_SEL is low, then the DLPC300 slave address is 1Bh. If I2C-ADDR_SEL pin is high, then the DLPC300 slave address is 1Dh. See the DLPC300 Programmer's Guide (DLPU004) for detailed information about these operations.
Table 2 provides a description for active signals used by the DLPC300 to support the I2C interface.
|SCL||I2C clock. Bidirectional open-drain signal|
|SDA||I2C data. Bidirectional open-drain signal|
The data Interface is a digital video input port with up to 24-bit RGB, and has a nominal I/O voltage of 3.3 V. The data interface also supports a 24-bit BT656 video interface. As shown in Figure 15 (system block diagram), the data Interface can be configured to connect to an external processor or a video decoder device through an 8-, 16-, 18-, or 24-bit parallel interface.
Table 3 provides a description of the signals associated with the data interface.
|PDATA(23:0)||24-bit data inputs (8 bits for each of the red, green, and blue channels)|
|PCLK||Pixel clock; all input signals on data interface are synchronized with this clock.|
|DATAEN||Input data valid|
|PDM||Parallel data mask|
Maximum and minimum input timing specifications are provided in Parallel Interface Frame Timing Requirements and Parallel Interface General Timing Requirements. The mapping of the red-, green-, and blue-channel data bits is shown in Figure 12.
There are two primary output interfaces: illumination driver control interface and sync outputs.
An illumination interface is provided that supports up to a three (3) channel LED driver.
The illumination interface provides signals that support: LED driver enable, LED enable, LED enable select, and PWM signals to control the LED current.
Table 4 describes the active signals for the illumination interface.
|LEDDRV_ON||LED driver master enable|
|LED_SEL(1:0)||Red, Green, or Blue LED enable select|
|RED_EN||Red LED enable|
|GREEN_EN||Green LED enable|
|BLUE_EN||Blue LED enable|
|RPWM||Red LED PWM signal used to control the LED current|
|GPWM||Green LED PWM signal used to control the LED current|
|BPWM||Blue LED PWM signal used to control the LED current|
The DLP3000 WVGA chipset relies on the use of mobile DDR SDRAM to store DMD formatted patterns. The SDRAM interface is a 16-bit wide bus and nominally operates at a frequency of 166 MHz. The data bus is routed in a point-to-point fashion between the DLPC300 and the mDDR devices, where each data line only makes a single connection between the DLPC300 and the mDDR device.
Listed below are the compatibility requirements for the mDDR:
SDRAM memory Type: Mobile DDR
Size: 128 M-bit minimum. DLPC300 can only address 128 Mb . Use of larger memories requires bit A13 to be grounded
Organization: N x 16-bits wide with 4 equally sized banks
Burst Length: 4
Refresh period: ≥ 64 ms
Speed Grade tCK: 6 ns max
CAS Latency (CL): 3 clocks
tRCD: 3 clocks
tRP: 3 clocks
|MEM_A(12:0)||13-bit address bus|
|MEM_BA(1:0)||Bank select signals|
|MEM_CAS||Column address strobe|
|MEM_RAS||Row address strobe|
|MEM_LDQS||R/W data strobe for lower byte|
|MEM_LDM||Write data mask for lower byte|
|MEM_UDQS||R/W data strobe for upper byte|
|MEM_UDM||Write data mask for upper byte|
|MEM_DQ(15:0)||16-bit data bus|
|MEM_CLK_N||Negative signal of the differential clock pair|
|MEM_CLK_P||Positive signal of the differential clock pair|
Table 6 shows the mDDR DRAM devices recommended for use with the DLPC300.
|Vendor||Part Number(2)||Size||Organization||Speed Grade(3)
|CAS Latency (CL)
|Elpida||EDD25163HBH-6ELS-F(5)||256 Mb||16M × 16||6 ns||3, 3, 3|
|Samsung||K4X56163PN-FGC6(5)||256 Mb||16M × 16||6 ns||3, 3, 3|
|Micron||MT46H16M16LFBF-6IT:H||256 Mb||16M × 16||6 ns||3, 3, 3|
|Micron||MT46H32M16LF-6 IT:B||512 MB||32M × 16||6 ns||3, 3, 3|
|Micron||MT46H32M16LFBF-6:B||512 MB||32M × 16||6 ns||3, 3, 3|
|Micron||MT46H64M16LFCK-5:A(5)||1 Gb||64M × 16||6 ns||3, 3, 3|
|Hynix||H5MS2562JFR-J3M||256 Mb||16M × 16||6 ns||3, 3, 3|
|Winbond||W947D6HBHX6E||128 Mb||8M × 16||6 ns||3, 3, 3|
DLPC300 uses an external 16-Mb SPI serial flash slave memory device for configuration support. The contents of this flash memory can be downloaded from the DLPC300 product folder. The DLPC300 uses a single SPI interface, employing SPI mode 0 protocol, operating at a nominal frequency of 33.3 MHz.
When RESET is released, the DLPC300 reads the contents of the serial flash memory and executes an auto-initialization routine. During this time, INIT_DONE is set high to indicate auto-initialization is busy. Upon completion of the auto-initialization routine, the DLPC300 sets INIT_DONE low to indicate that the auto-initialization routine successfully completed.
The DLPC300 should support any flash device that is compatible with standard SPI mode 0 protocol and meet the timing requirement shown in Flash Interface Timing Requirements. However, the DLPC300 does not support the normal (slow) read opcode, and thus cannot automatically adapt protocol and clock rate based on the electronic signature ID of the flash. The flash instead uses a fixed SPI clock and assumes certain attributes of the flash have been ensured by PCB design. The DLPC300 also assumes the flash supports address auto-incrementing for all read operations. Table 7 lists the specific Instruction opcode and timing compatibility requirements for a DLPC300-compatible flash.
|SPI Flash Command||Opcode (hex)||Address Bytes||Dummy Bytes||Clock Rate|
|Fast READ (single output)||0x0B||3||1||33.3 MHz|
|All others||Can vary||Can vary||Can vary||33.3 MHz|
The DLPC300 does not have any specific page, block or sector size requirements except that programming through the I2C interface requires the use of page-mode programming. However, if the user would like to dedicate a portion of the serial flash for storing external data (such as calibration data) and access it through the DLPC300's I2C interface, then the minimum sector size must be considered, as it drives minimum erase size.
Note that the DLPC300 does not drive the HOLD (active-low hold) or WP (active-low write protect) pins on the flash device, and thus these pins should be tied to a logic high on the PCB by an external pullup.
The DLPC300 supports 1.8-, 2.5-, or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the corresponding voltage.
Table 8 describes the signals used to support this interface.
|SPIDOUT||Serial configuration flash data output (from DLPC300 to flash)|
|SPIDIN||Serial configuration flash data input (from flash to DLPC300)|
|SPICLK||Serial configuration flash clock|
|SPICS0||Serial configuration flash chip select|
Table 9 contains a list of 1.8-, 2.5-, and 3.3-V compatible SPI serial flash devices supported by DLPC300.
|Density||Vendor||Part Number(2)||Supply Voltage Supported(3)||Min Chip Select High Time (tCSH)||Max Fast Read FREQ(4)||Compatible With OpCode and Timing in Table 7|
|4 Mb||Macronix||MX25U4035||1.65 V–2 V||30 ns||40 MHz||Yes|
|8 Mb||Macronix||MX25U8035||1.65 V–2 V||30 ns||40 MHz||Yes|
|16 Mb||Winbond||W25Q16BLxxxx||2.3 V–3.6 V||100 ns||50 MHz||Yes|
|8 Mb||Macronix||MX25L8005ZUx-xxG||2.7 V–3.6 V||100 ns||66 MHz||Yes|
The DLPC300 requires a 16.667-MHz 1.8-V external input from an oscillator. This signal is the DLP3000 WVGA chipset reference clock from which the majority of the interfaces derive their timing. This includes mDDR SDRAM, DMD interfaces, and serial interfaces.
See Specifications for reference clock specifications.
The DLPC300 provides the DMD pattern data to the DMD over a double data rate (DDR) interface.
Table 10 describes the signals used for this interface.
|DLPC300 SIGNAL NAME||DLP3000 SIGNAL NAME|
The DLPC300 provides the control data to the DMD over a serial bus.
Table 11 describes the signals used for this interface.
|DMD_SAC_BUS||SAC_BUS||DMD stepped-address control (SAC) bus data|
|DMD_SAC_CLK||SAC_CLK||DMD stepped-address control (SAC) bus clock|
|DMD_LOADB||LOADB||DMD data load signal|
|DMD_SCTRL||SCTRL||DMD data serial control signal|
|DMD_TRC||TRC||DMD data toggle rate control|
The DLPC300 controls the micromirror clock pulses in a manner to ensure proper and reliable operation of the DMD.
Table 12 describes the signals used for this interface.
|DLPC300 SIGNAL NAME||DLP3000 SIGNAL NAME||DESCRIPTION|
|DMD_DRC_BUS||DRC_BUS||DMD reset control serial bus|
|DMD_DRC_OE||DRC_OE||DMD reset control output enable|
|DMD_DRC_STRB||DRC_STRB||DMD reset control strobe|
Unless otherwise noted, 10 ns is the maximum recommended 20% to 80% rise/fall time to avoid input buffer oscillation. This applies to all DLPC300 input signals. However, the PARK input signal includes an additional small digital filter that ignores any input-buffer transitions caused by a slower rise or fall time for up to 150 ns.
Figure 15 shows a typical embedded system application using the DLPC300. In this configuration, the DLPC300 controller supports a 24-bit parallel RGB, typical of LCD interfaces, from the main processor chip. This system supports both still and motion video sources. For this configuration, the controller only supports periodic sources. This is ideal for motion video sources, but can also be used for still images by maintaining periodic syncs but only sending a frame of data when needed. The still image must be fully contained within a single video frame and meet frame timing constraints. The DLPC300 refreshes the displayed image at the source frame rate and repeats the last active frame for intervals in which no new frame has been received.
An optional FPGA (see the DLPR300 software folder) can be added to the system to manage the bit-planes stored in the mDDR. The mDDR accommodates four 608 × 684 images of 24-bit RGB data or 96 bit-planes (24 bit-planes × 4 images). By preloading the mDDR with these bit-planes, faster frame rates can be achieved. The 96 bit-plane buffer is arranged in a circular buffer style, meaning that the last bit-plane addition to the buffer replaces the oldest stored bit-plane. Figure 16 shows the overall system with the optional FPGA.
With this FPGA, the pattern frame rate can be calculated with Equation 1.
Table 13 shows the maximum pattern rate that can be achieved by using a single FPGA internal buffer in continuous mode.
|Color Mode||Maximum Number of Patterns||Maximum Pattern Rate|
|Monochrome||1 bit per pixel||96||4000 Hz|
|2 bits per pixel||48||1100 Hz|
|3 bits per pixel||32||590 Hz|
|4 bits per pixel||24||550 Hz|
|5 bits per pixel||16||450 Hz|
|6 bits per pixel||16||365 Hz|
|7 bits per pixel||12||210 Hz|
|8 bits per pixel||12||115 Hz|
The digital RGB input interface operates at 1.8 V, 2.5 V, or 3.3 V nominal, depending on the VCC_INTF supply. The SPI flash interface operates at 1.8 V, 2.5 V, or 3.3 V nominal, depending on the VCC_FLSH supply. The DMD and mDDR interface operates at 1.8 V nominal (VCC18). The core transistors operate at 1 V nominal (VDD10). The analog PLL operates at 1 V nominal (VDD_PLL).