DLPS253B September   2024  – August 2025 DLPC8445 , DLPC8455

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     6
    2. 4.1  Initialization, Board Level Test, and Debug
    3. 4.2  V-by-One Interface Input Data and Control
    4. 4.3  FPD Link Port(s) Input Data and Control (Not Supported in DLPC8445, DLPC8445V, and DLPC8455)
    5. 4.4  DSI Input Data and Clock (Not Supported in DLPC8445, DLPC8445V, and DLPC8455)
    6. 4.5  DMD SubLVDS Interface
    7. 4.6  DMD Reset and Low-Speed Interfaces
    8. 4.7  Flash Interface
    9. 4.8  Peripheral Interfaces
    10. 4.9  GPIO Peripheral Interface
    11. 4.10 Clock and PLL Support
    12. 4.11 Power and Ground
    13. 4.12 I/O Type Subscript Definition
    14. 4.13 Internal Pullup and Pulldown Characteristics
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2.     22
    3. 5.2  ESD Ratings
    4. 5.3  Recommended Operating Conditions
    5. 5.4  Thermal Information
    6. 5.5  Power Electrical Characteristics
    7. 5.6  Pin Electrical Characteristics
    8. 5.7  DMD SubLVDS Interface Electrical Characteristics
    9.     29
    10. 5.8  DMD Low-Speed Interface Electrical Characteristics
    11.     31
    12. 5.9  V-by-One Interface Electrical Characteristics
    13. 5.10 USB Electrical Characteristics
    14.     34
    15. 5.11 System Oscillator Timing Requirements
    16.     36
    17. 5.12 Power Supply and Reset Timing Requirements
    18.     38
    19. 5.13 V-by-One Interface General Timing Requirements
    20.     40
    21. 5.14 Flash Interface Timing Requirements
    22.     42
    23. 5.15 Source Frame Timing Requirements
    24.     44
    25. 5.16 Synchronous Serial Port Interface Timing Requirements
    26.     46
    27. 5.17 I2C Interface Timing Requirements
    28. 5.18 Programmable Output Clock Timing Requirements
    29. 5.19 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    30.     50
    31. 5.20 DMD Low-Speed Interface Timing Requirements
    32.     52
    33. 5.21 DMD SubLVDS Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 V-by-One Interface
      3. 6.3.3 DMD (SubLVDS) Interface
      4. 6.3.4 Serial Flash Interface
      5. 6.3.5 GPIO Supported Functionality
        1.       63
        2.       64
      6. 6.3.6 Debug Support
  8. 7 Power Supply Recommendations
    1. 7.1 System Power-Up and Power-Down Sequence
    2. 7.2 DMD Fast Park Control (PARKZ)
    3. 7.3 Power Supply Management
    4. 7.4 Hotplug Usage
    5. 7.5 Power Supplies for Unused Input Source Interfaces
    6. 7.6 Power Supplies
      1. 7.6.1 Power Supplies DLPA3085 or DLPA3082
  9. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Layout Guideline for DLPC8445, DLPC8445V, or DLPC8455 Reference Clock
        1. 8.1.1.1 Recommended Crystal Oscillator Configuration
      2. 8.1.2 V-by-One Interface Layout Considerations
      3. 8.1.3 DMD Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 8.1.4 Power Supply Layout Guidelines
    2. 8.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Device Nomenclature
      1. 9.5.1 Device Markings
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
      1. 9.8.1 Video Timing Parameter Definitions
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.3 DMD Maximum Pin-to-Pin, PCB Interconnects Etch Lengths

Table 8-5 Maximum Pin-to-Pin PCB Interconnect Recommendations
DMD BUS SIGNAL(1)(2)SIGNAL INTERCONNECT TOPOLOGYUNIT
SINGLE-BOARD SIGNAL ROUTING LENGTHMULTI-BOARD SIGNAL ROUTING LENGTH
DMD_HS_CLK_P
DMD_HS_CLK_N		10.0
(254)		See (3)in
(mm)
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N		10.0
(254)		See (3)in
(mm)
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_LS_CLK10.0
(254)		See (3)in
(mm)
DMD_LS_WDATA10.0
(254)		See (3)in
(mm)
DMD_LS_RDATA10.0
(254)		See (3)in
(mm)
DMD_DEN_ARSTZ10.0
(254)		See (3)in
(mm)
(1) The maximum signal routing length includes escape routing.
(2) Multiboard DMD routing length is more restricted due to the impact of the connector.
(3) Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate the controller IBIS model (found under the Tools & Software tab of the controller web page) so that routing lengths do not violate signal requirements.
Table 8-6 High-Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING(1)(2)(3)
INTERFACESIGNAL GROUPREFERENCE SIGNALMAX MISMATCH(4)UNIT
DMD(5)DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N		DMD_HS_CLK_P
DMD_HS_CLK_N		±1.0
(±25.4)		in
(mm)
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMDDMD_HS_WDATA_x_PDMD_HS_WDATA_x_N±0.025
(±0.635)		in
(mm)
DMDDMD_HS_CLK_PDMD_HS_CLK_N±0.025
(±0.635)		in
(mm)
DMDDMD_LS_WDATA
DMD_LS_RDATA		DMD_LS_CLK±0.2
(±5.08)		in
(mm)
DMDDMD_DEN_ARSTZN/AN/Ain
(mm)
(1) The length-matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC8445 controller or the DMD requires no additional consideration.
(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data lines.
(3) DMD LS signals are single-ended.
(4) Mismatch variance for a signal group is always with respect to the reference signal.
(5) DMD HS data lines are differential; thus, these specifications are pair-to-pair.
Table 8-7 Signal Requirements
PARAMETERREFERENCEREQUIREMENT
Source series terminationDMD_LS_WDATARequired 33Ω ±10%
DMD_LS_CLKRequired 33Ω ±10%
DMD_DEN_ARSTZAcceptable
DMD_LS_RDATARequired 30.1Ω ±10%
DMD_HS_WDATA_x_yNot acceptable
DMD_HS_CLK_yNot acceptable
Endpoint terminationDMD_LS_WDATANot acceptable
DMD_LS_CLKNot acceptable
DMD_DEN_ARSTZNot acceptable
DMD_LS_RDATANot acceptable
DMD_HS_WDATA_x_yNot acceptable
DMD_HS_CLK_yNot acceptable
PCB impedanceDMD_LS_WDATA50Ω ±10%
DMD_LS_CLK50Ω ±10%
DMD_DEN_ARSTZ50Ω ±10%
DMD_LS_RDATA50Ω ±10%
DMD_HS_WDATA_x_y100Ω ±10%
DMD_HS_CLK_y100Ω ±10%
Signal typeDMD_LS_WDATASDR (single data rate) referenced to DMD_LS_DCLK
DMD_LS_CLKSDR referenced to DMD_LS_DCLK
DMD_DEN_ARSTZSDR
DMD_LS_RDATASDR referenced to DMD_LS_DLCK
DMD_HS_WDATA_x_ySubLVDS
DMD_HS_CLK_ySubLVDS