SLLSEC6E September 2012 – June 2019 DP83848-EP
PRODUCTION DATA.
BIT | BIT NAME | DEFAULT | DESCRIPTION |
---|---|---|---|
15 | Reset | 0, RW/SC | Reset: |
1 = Initiate software Reset/Reset in Process. | |||
0 = Normal operation. | |||
This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. | |||
14 | Loopback | 0, RW | Loopback: |
1 = Loopback enabled. | |||
0 = Normal operation. | |||
The loopback function enables MII transmit data to be routed to the MII receive data path. | |||
Setting this bit may cause the descrambler to lose synchronization and produce a 500-µs dead time before any valid data will appear at the MII receive outputs. | |||
13 | Speed Selection | Strap, RW | Speed Select: |
When auto-negotiation is disabled writing to this bit allows the port speed to be selected. | |||
1 = 100 Mbps. | |||
0 = 10 Mbps. | |||
12 | Auto-Negotiation Enable | Strap, RW | Auto-Negotiation Enable: |
Strap controls initial value at reset. | |||
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. | |||
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. | |||
11 | Power Down | 0, RW | Power Down: |
1 = Power down. | |||
0 = Normal operation. | |||
Setting this bit powers down the PHY. Only the register block is enabled during a power down condition. This bit is OR’d with the input from the PWR_DOWN/INT pin. When the active low PWR_DOWN/INT pin is asserted, this bit will be set. | |||
10 | Isolate | 0, RW | Isolate: |
1 = Isolates the Port from the MII with the exception of the serial management. | |||
0 = Normal operation. | |||
9 | Restart Auto-Negotiation | 0, RW/SC | Restart Auto-Negotiation: |
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. | |||
0 = Normal operation. | |||
8 | Duplex Mode | Strap, RW | Duplex Mode: |
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected. | |||
1 = Full Duplex operation. | |||
0 = Half Duplex operation. | |||
7 | Collision Test | 0, RW | Collision Test: |
1 = Collision test enabled. | |||
0 = Normal operation. | |||
When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the de-assertion of TX_EN. | |||
6:00 | RESERVED | 0, RO | RESERVED: Write ignored, read as 0. |