SLVSM71 November   2026 DP83C8512

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 DP83C8512x Device Comparison
  6. 5 Pin Configuration and Function
    1. 5.1 Pin Configuration and Functions (DP83C8512xM)
    2. 5.2 Pin Configuration and Functions (DP83C8512xRL)
    3. 5.3 Pin Configuration and Functions (DP83C8512xRF)
  7. 6 Specifications
    1. 6.1 Thermal Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 7.3.2  Auto-MDIX Resolution
      3. 7.3.3  Energy Efficient Ethernet
        1. 7.3.3.1 EEE Overview
        2. 7.3.3.2 EEE Negotiation
      4. 7.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 7.3.5  Wake-on-LAN Packet Detection
        1. 7.3.5.1 Magic Packet Structure
        2. 7.3.5.2 Magic Packet Example
        3. 7.3.5.3 Wake-on-LAN Configuration and Status
      6. 7.3.6  Low-Power Modes
        1. 7.3.6.1 Active Sleep
        2. 7.3.6.2 IEEE Power-Down
        3. 7.3.6.3 Deep Power Down State
      7. 7.3.7  Clock Output
      8. 7.3.8  Media Independent Interface (MII)
      9. 7.3.9  Reduced Media Independent Interface (RMII)
      10. 7.3.10 RMII Repeater Mode
      11. 7.3.11 Serial Management Interface
        1. 7.3.11.1 Extended Register Space Access
        2. 7.3.11.2 Write Address Operation
        3. 7.3.11.3 Read Address Operation
        4. 7.3.11.4 Write (No Post Increment) Operation
        5. 7.3.11.5 Read (No Post Increment) Operation
        6. 7.3.11.6 Example Write Operation (No Post Increment)
      12. 7.3.12 100BASE-TX
        1. 7.3.12.1 100BASE-TX Transmitter
          1. 7.3.12.1.1 Code-Group Encoding and Injection
          2. 7.3.12.1.2 Scrambler
          3. 7.3.12.1.3 NRZ to NRZI Encoder
          4. 7.3.12.1.4 Binary to MLT-3 Converter
        2. 7.3.12.2 100BASE-TX Receiver
      13. 7.3.13 10BASE-Te
        1. 7.3.13.1 Squelch
        2. 7.3.13.2 Normal Link Pulse Detection and Generation
        3. 7.3.13.3 Jabber
        4. 7.3.13.4 Active Link Polarity Detection and Correction
      14. 7.3.14 Loopback Modes
        1. 7.3.14.1 Near-end Loopback
        2. 7.3.14.2 MII Loopback
        3. 7.3.14.3 PCS Loopback
        4. 7.3.14.4 Digital Loopback
        5. 7.3.14.5 Analog Loopback
        6. 7.3.14.6 Far-End (Reverse) Loopback
      15. 7.3.15 BIST Configurations
      16. 7.3.16 LED and GPIO Configuration
    4. 7.4 DP83C8512x Configuration
      1. 7.4.1 Hardware Bootstraps Configuration
        1. 7.4.1.1 DP83C8512x Hardware Configurations
  9. 8 DP83C8512x Registers
    1. 8.1 DP83C8512Fx Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 9.2.2 Transformer Recommendations
      3. 9.2.3 Capacitive DC Blocking
      4. 9.2.4 Design Requirements
        1. 9.2.4.1 Clock Requirements
          1. 9.2.4.1.1 Oscillator
          2. 9.2.4.1.2 Crystal
      5. 9.2.5 Detailed Design Procedure
        1. 9.2.5.1 MII Layout Guidelines
        2. 9.2.5.2 RMII Layout Guidelines
        3. 9.2.5.3 MDI Layout Guidelines
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Transformer Layout
        4. 9.4.1.4 Metal Pour
        5. 9.4.1.5 PCB Layer Stacking
          1. 9.4.1.5.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Pin Configuration and Functions (DP83C8512xM)

The DP83C8512xM supports the media-independent interface (MII) as specified in IEEE 802.3 Clause 22. The MII interface is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC.

Figure 5-1 DP83C8512xM
RHB Package
32-Pin QFN
(Top View)
Table 5-1 Pin Functions (DP83C8512xM)
PIN TYPE (1) DESCRIPTION
NAME NO

RBIAS

 1

A

 RBIAS (Bias resistor): A value 6.49kΩ with 1% precision connected to ground.
CEXT 2 A External Capacitor: Connect the CEXT pin through a 2.2nF capacitor to GND.

RD_M

 3

A

 Differential Receive Input (PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX specific signaling mode.
RD_P 4 A
TX_M 5 A Differential Transmit Output (PMD): These differential outputs are configured to either 10BASE-Te or 100BASE-TX signaling mode based on configuration selected for PHY.
TX_P 6 A
VDDA3V3 7 Power Input Analog Supply: 3.3V. For decoupling capacitor requirements, refer to Power Supply Decoupling Recommendations section of datasheet.
RX_DV 8 Reset: I, PD Active: O Receive Data Valid (MAC): This pin indicates valid data is present on the RX_D[3:0] for the MII mode.
RX_D0 9 Reset: I, PD Active: O Receive Data (MAC): Symbols received on the cable are decoded and presented on these pins synchronous to the rising edge of RX_CLK and contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is received in MII mode.
RX_D1 10 Reset: I, PD Active: O
RX_D2 11 Reset: I, PD Active: O
RX_D3 12 Reset: I, PD Active: O
RX_CLK 13 Reset: I, PD Active: O MII Receive Clock (MAC): MII Receive Clock provides a 25MHz reference clock for 100bps speed and a 2.5MHz reference clock for 10Mbps speed, which is derived from the received data stream.
VDDIO 14 Power I/O Supply Voltage: 3.3V or 1.8V. For decoupling capacitor requirements, refer to Power Supply Decoupling Recommendations section of datasheet.
TX_CLK 15 Reset: I, PD Active: O MII Transmit Clock (MAC): MII transmit clock provides a 25MHz reference clock for 100Mbps speed and a 2.5MHz reference clock for 10Mbps speed.
TX_D0 16 Reset: I, PD Active: I, PD Transmit Data (MAC): In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK.
TX_D1 17 Reset: I, PD Active: I, PD
TX_D2 18 Reset: I, PD Active: I, PD
TX_D3 19 Reset: I, PD Active: I, PD
TX_EN 20 Reset: I, PD Active: I, PD Transmit Enable (MAC): TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII mode. TX_EN is an active high signal.
RST_N 21 Reset: I, PU Active: I, PU Reset Low: RST_N pin is an active low reset input. Asserting this pin low for at least 25μs forces a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all the internal registers of the PHY to default value.
MDC 22 Reset: I, PD Active: I, PD Management Data Clock: Synchronous clock to the MDIO serial management input/output data. This clock can be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz. There is no minimum clock rate.
MDIO 23 Reset: I, PU Active: I/O, PU Management Data I/O: Bi-directional management data signal that can be sourced by the management station or the PHY. This pin has internal pullup resistor of 10kΩ. An external pullup resistor can be added if needed.
LED0 24 Reset: I, PD Active: O LED0: The LED indicates transmit and receive activity in addition to the status of the link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is active. The LED polarity is auto-detected (Active Low/ Active High) based on external pull-up or pull-down on the pin.
LED1/CLKOUT 25 Reset: I, PU Active: O LED1/CLKOUT: This pin provides 25MHz reference clock from XI as default output after power-on reset (POR). The output is not affected by Resets allowing Application to reset PHY without impacting other system getting impacted. The output clock switches off only by Deep Power Down. The pin can be configured to act as LED1 using Strap6 or register configuration. The LED is ON when link is 100Mbps, and remains OFF if link is 10Mbps or no link. The LED polarity is auto-detected (Active Low/ Active High) based on external pull-up or pull-down on the pin. This strap only latches on power-up and not on pin reset.
CRS 26 Reset: I, PD Active: O Carrier Sense (MAC): In MII mode this pin is asserted high when the receive or transmit medium is non-idle. Carrier sense and receive data valid.
COL 27 Reset: I, PD Active: O Collision Detect (MAC): In MII mode this pin is always LOW in Full Duplex mode. In Half Duplex mode, COL is asserted HIGH only when both transmit and receive media are non-idle.
RX_ER 28 Reset: I, PD Active: O Receive Error (MAC): This pin indicates that an error symbol has been detected within a received packet in the MII mode. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. RX_ER is asserted high for every reception error, including errors during Idle. This strap only latches on power-up and not on pin reset.
NC 29 A No Connect.
NC 30 A No Connect, can be driven with 3.3V
XI 31 A Crystal or Oscillator Input Clock: 25MHz ± 50ppm tolerance crystal or oscillator clock input.
XO 32 A Crystal Output: XO pin is used for crystal only. Leave this pin floating when a CMOS-level oscillator is connected to XI.
(1) I = Input, O = Output, I/O = Input/Ouput, A = Analog, PU or PD = Internal pullup or pulldown: Hardware bootstrap configuration