SLVSM70 November   2026 DP83C8522

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 DP83C8522x Device Comparison
  6. 5 Pin Configuration and Function
    1. 5.1 Pin Configuration and Functions (DP83C8522xM)
    2. 5.2 Pin Configuration and Functions (DP83C8522xRL)
    3. 5.3 Pin Configuration and Functions (DP83C8522xRF)
  7. 6 Specifications
    1. 6.1 Thermal Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 7.3.2  Auto-MDIX Resolution
      3. 7.3.3  Energy Efficient Ethernet
        1. 7.3.3.1 EEE Overview
        2. 7.3.3.2 EEE Negotiation
      4. 7.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 7.3.5  Wake-on-LAN Packet Detection
        1. 7.3.5.1 Magic Packet Structure
        2. 7.3.5.2 Magic Packet Example
        3. 7.3.5.3 Wake-on-LAN Configuration and Status
      6. 7.3.6  Low-Power Modes
        1. 7.3.6.1 Active Sleep
        2. 7.3.6.2 IEEE Power-Down
        3. 7.3.6.3 Deep Power Down State
      7. 7.3.7  Clock Output
      8. 7.3.8  Media Independent Interface (MII)
      9. 7.3.9  Reduced Media Independent Interface (RMII)
      10. 7.3.10 RMII Repeater Mode
      11. 7.3.11 Serial Management Interface
        1. 7.3.11.1 Extended Register Space Access
        2. 7.3.11.2 Write Address Operation
        3. 7.3.11.3 Read Address Operation
        4. 7.3.11.4 Write (No Post Increment) Operation
        5. 7.3.11.5 Read (No Post Increment) Operation
        6. 7.3.11.6 Example Write Operation (No Post Increment)
      12. 7.3.12 100BASE-TX
        1. 7.3.12.1 100BASE-TX Transmitter
          1. 7.3.12.1.1 Code-Group Encoding and Injection
          2. 7.3.12.1.2 Scrambler
          3. 7.3.12.1.3 NRZ to NRZI Encoder
          4. 7.3.12.1.4 Binary to MLT-3 Converter
        2. 7.3.12.2 100BASE-TX Receiver
      13. 7.3.13 10BASE-Te
        1. 7.3.13.1 Squelch
        2. 7.3.13.2 Normal Link Pulse Detection and Generation
        3. 7.3.13.3 Jabber
        4. 7.3.13.4 Active Link Polarity Detection and Correction
      14. 7.3.14 Loopback Modes
        1. 7.3.14.1 Near-end Loopback
        2. 7.3.14.2 MII Loopback
        3. 7.3.14.3 PCS Loopback
        4. 7.3.14.4 Digital Loopback
        5. 7.3.14.5 Analog Loopback
        6. 7.3.14.6 Far-End (Reverse) Loopback
      15. 7.3.15 BIST Configurations
      16. 7.3.16 Cable Diagnostics
        1. 7.3.16.1 Time Domain Reflectometry (TDR)
      17. 7.3.17 LED and GPIO Configuration
    4. 7.4 DP83C8522x Configuration
      1. 7.4.1 Hardware Bootstraps Configuration
        1. 7.4.1.1 DP83C8522x Hardware Configurations
  9. 8 Register Maps
    1. 8.1 DP83C8522x Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 9.2.2 Transformer Recommendations
      3. 9.2.3 Capacitive DC Blocking
      4. 9.2.4 Design Requirements
        1. 9.2.4.1 Clock Requirements
          1. 9.2.4.1.1 Oscillator
          2. 9.2.4.1.2 Crystal
      5. 9.2.5 Detailed Design Procedure
        1. 9.2.5.1 MII Layout Guidelines
        2. 9.2.5.2 RMII Layout Guidelines
        3. 9.2.5.3 MDI Layout Guidelines
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Transformer Layout
        4. 9.4.1.4 Metal Pour
        5. 9.4.1.5 PCB Layer Stacking
          1. 9.4.1.5.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DP83C8522x supports 10BASE-Te, 100BASE-TX Ethernet protocols in real-time industrial Ethernet systems.

The DP83C8522x supports both the standard Ethernet mode and multiple other industrial Ethernet fieldbus applications with the additional features and hardware bootstraps configuration.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)

DP83826AE/I

 VQFN (32) 5.00mm × 5.00mm

DP83826E/I

VQFN (32)

5.00mm × 5.00mm

DP83822HF/IF/H/I

VQFN (32)

 5.00mm × 5.00mm
DP83C8201FE/I VQFN (32) 5.00mm × 5.00mm

DP83C8512E/I

VQFN (32)

 5.00mm × 5.00mm

DP83C8522E/I

 VQFN (32) 5.00mm × 5.00mm

DP83C1111E/I

 VQFN (32) 5.00mm × 5.00mm

DP83825I

WQFN (24)

 3.00mm × 3.00mm
(1) For all available packages, see the orderable addendum at the end of the datasheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
Device Information
PART NUMBER ATTRIBUTES

DP83826AE/I
  • Enhanced EMC
  • Low latency
  • EtherCAT compliant
  • Multisource, pin and package compatible

DP83826E/I
  • Low latency
  • EtherCAT compliant
  • Multisource, pin and package compatible

DP83822HF/IF/H/I
  • -40°C to 125°C temperature support
  • Fiber and RGMII support
DP83C8201FE/I
  • Multisource, pin and package compatible

DP83C8512E/I
  • Multisource, pin and package compatible

DP83C8522E/I
  • Multisource, pin and package compatible

DP83C1111E/I
  • Multisource, pin and package compatible

DP83825I
  • Small size
  • Cost optimized
DP83C8522 Simplified Application Simplified Application