SNLS663A December   2021  – December 2025 DP83TC814R-Q1 , DP83TC814S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Electrostatic Discharge Sensing
        3. 7.3.1.3 Time Domain Reflectometry
        4. 7.3.1.4 Voltage Sensing
        5. 7.3.1.5 BIST and Loopback Modes
          1. 7.3.1.5.1 Data Generator and Checker
          2. 7.3.1.5.2 xMII Loopback
          3. 7.3.1.5.3 PCS Loopback
          4. 7.3.1.5.4 Digital Loopback
          5. 7.3.1.5.5 Analog Loopback
          6. 7.3.1.5.6 Reverse Loopback
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Reset
      3. 7.4.3 Standby
      4. 7.4.4 Normal
      5. 7.4.5 Media Dependent Interface
        1. 7.4.5.1 100BASE-T1 Leader and 100BASE-T1 Follower Configuration
        2. 7.4.5.2 Auto-Polarity Detection and Correction
        3. 7.4.5.3 Jabber Detection
        4. 7.4.5.4 Interleave Detection
      6. 7.4.6 MAC Interfaces
        1. 7.4.6.1 Media Independent Interface
        2. 7.4.6.2 Reduced Media Independent Interface
        3. 7.4.6.3 Reduced Gigabit Media Independent Interface
        4. 7.4.6.4 Serial Gigabit Media Independent Interface
      7. 7.4.7 Serial Management Interface
        1. 7.4.7.1 Direct Register Access
        2. 7.4.7.2 Extended Register Space Access
        3. 7.4.7.3 Write Operation (No Post Increment)
        4. 7.4.7.4 Read Operation (No Post Increment)
        5. 7.4.7.5 Write Operation (Post Increment)
        6. 7.4.7.6 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
  9. 8 Register Maps
    1. 8.1 Register Access Summary
    2. 8.2 DP83TC814 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Metal Pour
        4. 9.4.1.4 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.1.5.4 Digital Loopback
DP83TC814S-Q1 DP83TC814R-Q1 Digital Loopback With Data GeneratorFigure 7-5 Digital Loopback With Data Generator
DP83TC814S-Q1 DP83TC814R-Q1 Digital Loopback Without Data GeneratorFigure 7-6 Digital Loopback Without Data Generator

Digital Loopback loops back data prior to exiting the Digital and entering the AFE. Data received from the MAC on the transmit path is brought through the digital block within the PHY where data is then routed back to the MAC through the receive path. The DP83TC814 receive Analog circuitry is configured for isolation to prevent contention.

Enable Loopback

Write register 0x0016 = 0x0104

Enable Data Generator/Checker for MAC Side

Write register 0x0624 = 0x55BF

Write register 0x0619 = 0x1555

Check Incoming Data From MAC Side

Data can also be checked internally by reading registers 0x063C, 0x063D, 0x063E. The registers must be read together and in this order.

Enable Data Generator/Checker for Cable Side

Write register 0x0624 = 0x55BF

Write register 0x0619 = 0x0557

Check Data for Cable Side

  1. Write register 0x0620[1] = 1'b1
  2. Read register 0x620
    1. Bit [7:0] = Number of errors bytes received
    2. Bit [8] = PRBS checker lock status on incoming data (1'b1 indicates lock)
Repeat steps 1 and 2 to continuously check error status of incoming data stream.

Other System Requirements

Data generate by the internal PRBS is transmitted over the MDI and the MAC interface.