SNLS663A
December 2021 – December 2025
DP83TC814R-Q1
,
DP83TC814S-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagrams
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Diagnostic Tool Kit
7.3.1.1
Signal Quality Indicator
7.3.1.2
Electrostatic Discharge Sensing
7.3.1.3
Time Domain Reflectometry
7.3.1.4
Voltage Sensing
7.3.1.5
BIST and Loopback Modes
7.3.1.5.1
Data Generator and Checker
7.3.1.5.2
xMII Loopback
7.3.1.5.3
PCS Loopback
7.3.1.5.4
Digital Loopback
7.3.1.5.5
Analog Loopback
7.3.1.5.6
Reverse Loopback
7.3.2
Compliance Test Modes
7.3.2.1
Test Mode 1
7.3.2.2
Test Mode 2
7.3.2.3
Test Mode 4
7.3.2.4
Test Mode 5
7.4
Device Functional Modes
7.4.1
Power Down
7.4.2
Reset
7.4.3
Standby
7.4.4
Normal
7.4.5
Media Dependent Interface
7.4.5.1
100BASE-T1 Leader and 100BASE-T1 Follower Configuration
7.4.5.2
Auto-Polarity Detection and Correction
7.4.5.3
Jabber Detection
7.4.5.4
Interleave Detection
7.4.6
MAC Interfaces
7.4.6.1
Media Independent Interface
7.4.6.2
Reduced Media Independent Interface
7.4.6.3
Reduced Gigabit Media Independent Interface
7.4.6.4
Serial Gigabit Media Independent Interface
7.4.7
Serial Management Interface
7.4.7.1
Direct Register Access
7.4.7.2
Extended Register Space Access
7.4.7.3
Write Operation (No Post Increment)
7.4.7.4
Read Operation (No Post Increment)
7.4.7.5
Write Operation (Post Increment)
7.4.7.6
Read Operation (Post Increment)
7.5
Programming
7.5.1
Strap Configuration
7.5.2
LED Configuration
7.5.3
PHY Address Configuration
8
Register Maps
8.1
Register Access Summary
8.2
DP83TC814 Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Design Requirements
9.2.1.1
Physical Medium Attachment
9.2.1.1.1
Common-Mode Choke Recommendations
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Signal Traces
9.4.1.2
Return Path
9.4.1.3
Metal Pour
9.4.1.4
PCB Layer Stacking
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHA|36
MPQF611A
Thermal pad, mechanical data (Package|Pins)
RHA|36
QFND711
Orderable Information
snls663a_oa
snls663a_pm
1
Features
Open Alliance and IEEE 802.3bw 100BASE-T1 compliant
Passes Level IV emissions with Integrated LPF
SAE J2962-3 EMC compliant
Configurable I/O voltages: 3.3V, 2.5V, and 1.8V
MAC interfaces: MII, RMII, RGMII and SGMII
Optional separate voltage rail for MAC interface pins (3.3V, 2.5V, 1.8V)
AEC-Q100 qualified for automotive applications:
Temperature grade 1: –40°C to +125°C ambient operating temperature
±8kV HBM ESD for pins
12 and 13
IEC61000-4-2 ESD classification level 4 for pins
12 and 13
: ±8kV contact discharge
IEEE 1588 SFD support
TSN compliant with 802.3br frame pre-emption support
Low active power operation: < 230mW
Diagnostic tool kit
Signal Quality Indication (SQI)
Time Domain Reflectometry (TDR)
Electrostatic discharge sensor
Voltage sensor
PRBS Built-in Self-Test
Loopbacks
VQFN, wettable flank packaging
Functional Safety-Capable
Documentation available to aid in functional safety system design