5 Pin Configuration and Functions

RX_D3
RX_M

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the rising edge of RX_CLK. Data is considered valid when RX_DV is asserted. A data nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII mode. RX_D[3:2] are not used when in RMII Follower mode.

If the PHY is bootstrapped to RMII Leader mode, a 50MHz clock reference is automatically outputted on RX_D3. This clock must be fed to the MAC.

RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC. Use the strap resistors in RX_D3 pin in SGMII mode.

RX_D2
RX_P

RX_D1

RX_D0

Receive Clock: In MII and RGMII modes, the receive clock provides a 25MHz reference clock.

Unused in RMII and SGMII modes

Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used by the MAC in MII or RMII because the PHY automatically corrupts data on a receive error.

Unused in RGMII and SGMII modes

Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.

Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode. To set Pin 15 as CRS_DV, set 0x0551=0x0010 (Default).

RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of RX_CLK. To set Pin 15 as RX_DV, set 0x0551=0x0000.

Unused in SGMII mode

Transmit Clock: In MII mode, the transmit clock is a 25MHz output (50Ω Driver) and has constant phase referenced to the reference clock. In RGMII mode, this clock is sourced from the MAC layer to the PHY. A 25MHz clock must be provided (not required to have constant phase to the reference clock unless synchronous RGMII is enabled)

Unused in RMII and SGMII modes

Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit enable is presented prior to the rising edge of the reference clock. TX_EN indicates the presence of valid data inputs on TX_D[1:0].

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented prior to the falling edge of TX_CLK.

Unused in SGMII mode

Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode.

TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.

TX_D1
TX_P

TX_D0
TX_M

Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock can be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 20MHz. There is no minimum clock rate.

Management Data Input/Output: Bidirectional management data signal that can be sourced by the management station or the PHY. This pin requires a pullup resistor. In systems with multiple PHYs using same MDIO-MDC bus, a single pull-up resistor must be used on MDIO line.

Recommended to use a resistor between 2.2kΩ and 9kΩ.

MDIO/MDC Access is required to pass Open Alliance Compliance. See Section 7.3.2

Interrupt: Active-LOW output, which is asserted LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event. This pin can be configured as an Active-HIGH output using register 0x0011.

Interrupt status from Reg 12-13 is recommended to be read only when INT_N is LOW. This pin can also operate as Power-Down control where asserting this pin low puts the PHY in power down mode and asserting high puts the PHY in normal mode. This feature can also be enabled using the register 0x0011.

Reset: Active-LOW input, which initializes or reinitializes the PHY. Asserting this pin LOW for at least 1μs forces a reset process to occur. All internal registers reinitializes to the default states as specified for each bit in the Register Maps section. All bootstrap pins are resampled upon deassertion of reset.

Reference Clock Input (RMII): Reference clock 50MHz CMOS-level oscillator in RMII Follower mode. Reference clock 25MHz crystal or oscillator in RMII Leader mode.

Reference Clock Input (Other MAC Interfaces): Reference clock 25MHz crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating. This pin can also accept clock input from other devices like Ethernet MAC or another Ethernet PHY in daisy-chain operations.

Reference Clock Output: XO pin is used for crystal only. This pin must be left floating when a CMOS-level oscillator is connected to XI.

LED_0: Link Status LED. This pin can also be used as LED or clock output via Register selection.

LED_1: Link Status and BLINK for TX/RX Activity. This pin can also be used as LED or clock output via Strap/Register selection.

Clock Output: 25MHz reference clock in all modes except RMII Follower, which is 50MHz instead. This pin can also be used as LED or GPIO via Strap/Register selection. Program register<0x045F>=0x000F and register<0x0453>=0x0003 to disable switching on CLKOUT pin

Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE 802.3bw compliant.

Ground Escape: Optional ground escape pins. These pins can be connected to ground to optimize PCB layout. These pins are not substitute for power ground connection to DAP. DAP must always be connected to power ground.

This pin can be left unconnected if not used.

Ground Escape: Optional ground escape pins. These pins can be connected to ground to optimize PCB layout. These pins are not substitute for power ground connection to DAP. DAP must always be connected to power ground.

This pin can be left unconnected if not used.