SLVSCU7A February   2016  – March 2016 DRV10970

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit and OCP
      2. 8.3.2 Thermal Shutdown
      3. 8.3.3 Rotor Lock Detection and Retry
      4. 8.3.4 Supply Undervoltage Condition (UVLO)
      5. 8.3.5 Sleep Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation in Trapezoidal Mode and Sinusoidal Mode
        1. 8.4.1.1 Trapezoidal Control Mode
        2. 8.4.1.2 Sinusoidal Pulse Wide Modulation (SPWM) Control Mode
      2. 8.4.2 Single Hall Sensor Operation
      3. 8.4.3 Adaptive Drive Angle Adjustment (ADAA) Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Hall Sensor Configuration and Connections
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The VM terminal should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of 10-µF rated for VM. Place this capacitor as close as possible to the VM pin with a thick trace or ground plane connection to the device GND pin.

The CRETRY capacitor should be placed as close to the RETRY pin as possible with a thick trace or ground plane connection to the device GND pin.

A low-ESR ceramic capacitor must be placed in between the CPN and CPP pins. TI recommends a value of 0.1-µF rated for VM. Place this component as close as possible to the pins.

A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. TI recommends a value of 1-µF rated for 16 V. Place this component as close as possible to the pins.

Bypass VINT to ground with 2.2-µF ceramic capacitors rated for 10 V. Place these bypassing capacitors as close to the pins as possible.

Because the GND pin carries motor current, take utmost care while planning grounding scheme, keep the ground potential difference between any two points less than 100 mV.

11.2 Layout Example

DRV10970 Layout_DRV10970.gif Figure 34. Layout Schematic