SLVSGJ9A May   2024  – October 2025 DRV7308

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Absolute Maximum Ratings
  7. 6 ESD Ratings
  8. 7 Recommended Operating Conditions
  9. 8 Thermal Information
  10. 9 Electrical Characteristics
  11. 10Timing Diagrams
  12. 11Typical Characteristics
  13. 12Detailed Description
    1. 12.1 Overview
    2. 12.2 Functional Block Diagram
    3. 12.3 Feature Description
      1. 12.3.1 Output Stage
      2. 12.3.2 Input Control Logic
      3. 12.3.3 ENABLE (EN) Pin Function
      4. 12.3.4 Temperature Sensor Output (VTEMP)
      5. 12.3.5 Brake Function
      6. 12.3.6 Slew Rate Control (SR)
      7. 12.3.7 Dead Time
      8. 12.3.8 Current Limit Functionality (ILIMIT)
      9. 12.3.9 Pin Diagrams
        1. 12.3.9.1 Four-Level Input Pin
        2. 12.3.9.2 Open-Drain Pin
        3. 12.3.9.3 Logic-Level Input Pin (Internal Pulldown)
    4. 12.4 Protections
      1. 12.4.1 GVDD Undervoltage Lockout
      2. 12.4.2 Bootstrap Undervoltage Lockout
      3. 12.4.3 Current Limit Protection
      4. 12.4.4 GaNFET Overcurrent Protection
      5. 12.4.5 Thermal Shutdown (OTS)
  14. 13Application and Implementation
    1. 13.1 Application Information
    2. 13.2 Typical Application
      1. 13.2.1 Application
        1. 13.2.1.1 Application Information
      2. 13.2.2 Application Curves
  15. 14Layout
    1. 14.1 Layout Guidelines
    2. 14.2 Layout Example
  16. 15Revision History
  17. 16Device and Documentation Support
    1. 16.1 Documentation Support
      1. 16.1.1 Related Documentation
    2. 16.2 Receiving Notification of Documentation Updates
    3. 16.3 Support Resources
    4. 16.4 Trademarks
    5. 16.5 Electrostatic Discharge Caution
    6. 16.6 Glossary
  18. 17Mechanical, Packaging, and Orderable Information
    1. 17.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Electrical Characteristics

TJ  = –40°C to 150°C, VGVDD = 15V, EN = High (unless otherwise noted). Typical limits apply for TA = 25°C, VGVDD = 15V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GaN POWER TRANSISTOR
RDS(ON) GaN transistor on resistance VGVDD = 15V, IOUTx = 1A,TJ = 25oC, 205 320 mΩ
RDS(ON) GaN transistor on resistance VGVDD = 15V, IOUTx = 1A, TJ = 150oC,  370 mΩ
VSD Third-quadrant mode source-drain voltage INx = 0V, ISD = 0.1A, TJ = 25oC 1.5 2.5 V
VSD Third-quadrant mode source-drain voltage INx = 0V, ISD = 4A, TJ = 25oC 2.8 V
QRR Reverse recovery charge VR = 300 V, ISD = 4 A, dISD/dt = 0.2 A/ns 0 nC
SWITCHING CHARACTERISTICS
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %) VVM= 300V, SR setting = 0 4 V/ns
SR Phase pin slew rate switching high to low (Falling from 80 % to 20 %) VVM= 300V, SR setting = 0 4 V/ns
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %) VVM= 300V, SR setting = 1 10 V/ns
SR Phase pin slew rate switching high to low (Falling from 80 % to 20 %) VVM= 300V, SR setting = 1 10 V/ns
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %) VVM= 300V, SR setting = 2 20 V/ns
SR Phase pin slew rate switching high to low (Falling from 80 % to 20 %) VVM= 300V, SR setting = 2 20 V/ns
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %) VVM= 300V, SR setting = 3 40 V/ns
SR Phase pin slew rate switching high to low (Falling from 80 % to 20 %) VVM= 300V, SR setting = 3 40 V/ns
tpd,on Propagation delay, turn on VINHx, VINLx = logic low to high, VVM = 300V, ID = 4A, SR = 0

 125 ns
tdelay,on Turn on delay time VINHx, VINLx = logic low to high, VVM = 300V, ID = 4A, SR = 0 75 ns
tpd,off Propagation delay, turn off VINHx, VINLx = logic high to low, VVM = 300V, ID = 4A, SR = 0

 135 ns
tdelay,off Turn off delay time VINHx, VINLx = logic high to low, VVM = 300V, ID = 4A, SR = 0 75 ns
tDEAD Output dead time (high to low) VVM = 300V, IOUTx = 4A, Current going out of phase node (OUTx)
SR = 0, 1		 40 ns
tDEAD Output dead time (high to low) VVM = 300V, IOUTx = 4A, Current going into phase node (OUTx), SR = 0 100 ns
tDEAD Output dead time (high to low) VVM = 300V, IOUTx = 4A, Current going into phase node (OUTx), SR = 1 or 2 or 3 100 ns
tDEAD Output dead time (low to high) VVM = 300V, IOUTx = 4A, Current going into phase node (OUTx) 40 ns
tstart Start up time  VGVDD > VGVDD_UV_ON. EN = low to high, INLx = 1, low side GaNFET turns ON

 2 ms
toff Device turn off time - to sleep VGVDD > VGVDD_UV_ON. EN = high to low 40 80 us
tclr_flt Time to clear any latched fault using EN EN = low pulse width 15 40 us
toff Device turn off time- gate driver off VGVDD > VGVDD_UV_ON. EN = high to low, INLx = 1, low side GaNFET turns OFF

 
 80 µs
GVDD POWER SUPPLY
IGVDD,Q GVDD operating current, driver enabled, no switching EN = High, VVM = 300V, INx = 0

 2.3 mA
IGVDD,3SW GVDD average operating current, driver enabled, GaN switching, No load at OUTx pins EN = High, Fsw = 20kHz, 3-half bridge switching at 50% complimentary PWM, VVM = 300V, VGVDD = 15V, SR = 0 3.7 mA
VGVDD_UV_R GVDD undervoltage threshold - rising GVDD rising 10 V
VGVDD_UV_F GVDD undervoltage threshold - falling GVDD falling 9 V
VGVDD_UV_HYS GVDD undervoltage detection hysteresis  GVDD rising to falling threshold 500 mV
tUVLO_GVDD GVDD undervoltage deglitch time 20 µs
BOOTSTRAP POWER SUPPLY
RDS_ BST Bootstrap rectifier on resistance VGVDD = 15V, VVM = 300V 30 Ω
ILMT_BST Bootstrap rectifier current limit EN = High, VGVDD = 15V, VVM = 300V, INLx = High, INHx = Low, VBOOTx - VOUTx = 12V 150 250 mA
IBST_PK Bootstrap rectifier peak transient current EN = High, VGVDD = 15V, VVM = 300V, INLx = High, INHx = Low, VBOOTx - VOUTx = 0 V 350 mA
IBST_Q Bootstrap quiescent current EN = High, INHx = Low, INLx = Low, VGVDD = 15V, VBOOTx - VOUTx = 12V

 100 145 µA
IBST_Q Bootstrap quiescent current EN = High, INHx = High, INLx = Low, VGVDD = 15V, VBOOTx - VOUTx = 12V

 350 µA
VBST_UV Bootstrap supply undervoltage  BOOTx rising 9 V
VBST_UV Bootstrap supply undervoltage BOOTx falling 8 V
VBST_UV_HYS Bootstrap supply undervoltage hysteresis 500 mV
tBST_UV Bootstrap supply undervoltage deglitch time 20 µs
LOGIC-LEVEL INPUTS (EN, INHx, INLx, BRAKE)
VIL Input logic low voltage INHx, INLx, BRAKE, EN 0.8 V
VIH Input logic high voltage INHx, INLx, BRAKE, EN 2.2 V
VHYS Input logic hysteresis INHx, INLx, BRAKE, EN 300 450 650 mV
IIL Input logic low current (INHx, INLx, BRAKE, EN) VI = 0 V -1 1 µA
IIL Input logic low current (BRAKE, EN) VI = 0 V -1 1 µA
RPD Input pulldown resistance INHx, INLx, EN 70 100 130 kΩ
RPD Input pulldown resistance BRAKE

 15 20 25 kΩ
tdeg Input logic deglitch time INHx, INLx

 
 25 50 ns
tdeg Input logic deglitch time EN 80 µs
tdeg Input logic deglitch time BRAKE

 1200 2000 ns
MULTI-LEVEL INPUT (SR)
RL1 SR setting = 0 Tied to GND 0 1 kΩ
RL2 SR setting = 1 Tied to GVDD 0 1 kΩ
RL3 SR setting =2 R tied to GND (R = 5 kΩ to 15 kΩ) 5 15  kΩ
RL4 SR setting = 3 R tied to GND (R = 40 kΩ to 100 kΩ) 40 100 kΩ
OPEN-DRAIN OUTPUTS (nFAULT)
VOL Output logic low voltage IOD = 5 mA 0.4 V
IOH Output logic high current VOD = 5 V -1 1 µA
COD Output capacitance 30 pF
GaN PREDRIVER PROTECTION
IOCP_GaN Low-side GaN FET overcurrent detection threshold VGVDD = 15V, VVM = 300V, TJ=25oC 7.5 24 A
IOCP_GaN Low-side GaN FET overcurrent detection threshold VGVDD = 15V, VVM = 300V, TJ=125oC 5 A
tOCP_GaN_BT Blanking time (including deglitch) VGVDD = 15V, VVM = 300V 150 ns
tOCP_GaN_PD Propagation delay (to FET turn off) VGVDD = 15V, VVM = 300V 50 ns
TSD_RISE Thermal shutdown rising Die temperature (TJ ) 145 165 185 oC
TSD_FALL Thermal shutdown falling Die temperature (TJ ) 125 145 165 oC
TSD_HYST Thermal shutdown hysteresis Die temperature (TJ ) 13 20 oC
CURRENT LIMIT COMPARATOR (ILIMIT)
Ib Input bias current (ILIMIT) VILIMIT = 0.5V 1 µA
Voff ILIMIT comparator input voltage offset VILIMIT = 1.0V ±2.5 mV
VILIMIT_DIS Minimum ILIMIT voltage to disable ILIMIT OCP 2.2 2.6 V
VILIMIT Operational voltage range at ILIMIT 2 V
tblank Over current detection blanking on all SLx inputs, from any INHx/INLx turn on/off 

 400 620 ns
tdeglitch Over current detection de-glitch time 190 330 ns
tfilter ILIMIT comparator input RC filter time (SLx) VSLx = 0 to 1V  step, VILIMIT = 0.63V

 250 450 ns
tfilter ILIMIT reference voltage input RC filter time (ILIMIT) VILIMIT = 1 to 0V step, VSLx = 0.37V 600 1000 ns
tpd_OFF Propagation delay time from ILIMIT over current detection to all GaN FETs turn off VILIMIT = 0.63V, VSLx = 0 to 1V  step, INx = constant 1.2 µs
tpd_FAULT Propagation delay time from ILIMIT over current detection to nFAULT pin report VILIMIT = 0.63V, VSLx = 0 to 1V  step, INx =constant 1 µs
OPERATIONAL AMPLIFIER
VLINEAR Output voltage swing RL = 10k to GND
 0.02 4.9 V
GBW Gain bandwidth product RL= 10k, G = +1 11 MHz
VSR_opamp Output voltage slew rate RL= 10k, G = +1 26 V/µs
tset Settling time to ±1% 2-V step , G = +1, CL = 130 pF, RL = 10k 0.4 µs
AOL Open-loop voltage gain 0.04 V < VAMPOUT < 4.8 V, RL = 10 kΩ to GND
 106 dB
φm Phase margin G = +1, RL = 10k
 60 o
VCOM Common mode input range 0 5 V
VOFF Input offset voltage error TA = –40°C to 125°C ±1 mV
VDRIFT Drift offset TA = –40°C to 125°C

 ±2 µV/oC
Ibias Input bias current VAMPIN- = VAMPIN+ = 2.5V ±100 nA
Ibias_off Input bias offset current VAMPIN- = VAMPIN+ = 2.5V

 ±10 nA
CMRR Common mode rejection ratio – 0.1 V < VCM < 5 V, TA = –40°C to 125°C 96 dB
ISC_opamp Short-circuit current ±20 mA
Zo Open-loop output impedance f = 5 MHz
 250 Ω
CL Capacitive load drive 130 pF
TEMPERATURE SENSOR
VT Temperature sense element output (VTEMP) voltage TA = 25°C 1.98 V
RT Minimum load resistance on VTEMP pin test condition of VT 90 kΩ
CT Maximum load capacitance at VTEMP pin test condition of VT 130 pF