SLVSHE0 August   2025 DRV8002-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 High-Side Drivers
        1. 7.4.1.1 High-side Driver Control
          1. 7.4.1.1.1 High-side Driver PWM Generator
          2. 7.4.1.1.2 Constant Current Mode
          3. 7.4.1.1.3 OUTx HS ITRIP Behavior
          4. 7.4.1.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.1.2 High-side Driver Protection Circuits
          1. 7.4.1.2.1 High-side Drivers Internal Diode
          2. 7.4.1.2.2 High-side Driver Short-circuit Protection
          3. 7.4.1.2.3 High-side Driver Overcurrent Protection
          4. 7.4.1.2.4 High-side Driver Open Load Detection
      2. 7.4.2 Half-bridge Drivers
        1. 7.4.2.1 Half-bridge Control
        2. 7.4.2.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.2.3 Half-bridge Register Control
        4. 7.4.2.4 Half-Bridge ITRIP Regulation
        5. 7.4.2.5 Half-bridge Protection and Diagnostics
          1. 7.4.2.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.2.5.2 Half-bridge Open Load Detection
          3. 7.4.2.5.3 Half-Bridge Overcurrent Protection
      3. 7.4.3 Gate Drivers
        1. 7.4.3.1 Input PWM Modes
          1. 7.4.3.1.1 Half-Bridge Control
          2. 7.4.3.1.2 H-Bridge Control
          3. 7.4.3.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.3.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.3.2.1  Smart Gate Driver
          2. 7.4.3.2.2  Functional Block Diagram
          3. 7.4.3.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.3.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.3.2.4.1 tDRIVE Calculation Example
          5. 7.4.3.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.3.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
          7. 7.4.3.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.3.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.3.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.3.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.3.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.3.2.10.1 STC Control Loop Setup
        3. 7.4.3.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.3.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.3.5 Gate Driver Protection Circuits
          1. 7.4.3.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.3.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.3.5.3 Offline Short-circuit and Open Load Detection (OOL and OSC)
      4. 7.4.4 Sense Output (IPROPI)
      5. 7.4.5 Protection Circuits
        1. 7.4.5.1 Fault Reset (CLR_FLT)
        2. 7.4.5.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.5.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.5.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.5.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.5.6 Thermal Clusters
        7. 7.4.5.7 Watchdog Timer
        8. 7.4.5.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8002-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IDRIVE Calculation Example
        2. 9.2.2.2 tDRIVE Calculation Example
        3. 9.2.2.3 Maximum PWM Switching Frequency
        4. 9.2.2.4 Current Shunt Amplifier Configuration
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Pre-Production Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 DRV8000-Q1_STATUS Registers

Table 8-3 lists the memory-mapped registers for the DRV8000-Q1_STATUS registers. All register offset addresses not listed in Table 8-3 should be considered as reserved locations and the register contents should not be modified.

Table 8-3 DRV8000-Q1_STATUS Registers
OffsetAcronymRegister NameSection
0hIC_STAT1Device status summary 1.Section 8.1.1
1hIC_STAT2Device status summary 2.Section 8.1.2
2hGD_STATGate driver status.Section 8.1.3
3hHB_STAT1Half-bridge overcurrent status.Section 8.1.4
4hHB_STAT2Half-bridge open-load status.Section 8.1.5
5hITRIP_STATITRIP status.Section 8.1.6
6hHS_STATHigh-side driver status.Section 8.1.7
7hHS_ITRIP_STATHigh-side ITRIP statusSection 8.1.8
8hSPARE_STAT2Spare status 2.Section 8.1.9

Complex bit access types are encoded to fit into small table cells. Table 8-4 shows the codes that are used for access types in this section.

Table 8-4 DRV8000-Q1_STATUS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

8.1.1 IC_STAT1 Register (Offset = 0h) [Reset = C000h]

IC_STAT1 is shown in Table 8-5.

Return to the Summary Table.

Main device status register for driver, supply and over temperature fault status. Also includes watchdog and ITRIP regulation fault status.

Table 8-5 IC_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
15SPI_OKR1h Indicates if a SPI communications fault has been detected.
0b = One or multiple of SCLK_FLT in the prior frames.
1b = No SPI fault has been detected.
14PORR1h Indicates power-on-reset condition.
0b = No power-on-reset condition detected.
1b = Power-on reset condition detected.
13FAULTR0h General Fault indicator. Indicates a device or driver fault has occurred.
0b = No fault.
1b = Fault detected.
12WARNR0h General warning indicator. Indicates a warning is present.
0b = No warning.
1b = Warning is present.
11GDR0h Logic OR of VDS and VGS fault indicators for gate driver.
10HBR0h Logic OR of overcurrent and open load fault indicators for half-bridges.
9RESERVEDR0h Reserved
8HSR0h Logic OR of overcurrent, short-circuit and open load fault indicators for integrated high-side drivers.
7PVDD_UVR0h Indicates undervoltage fault on PVDD pin.
6PVDD_OV_22VR0h Indicates overvoltage fault on PVDD pin greater than 22 V.
5VCP_UVR0h Indicates undervoltage fault on VCP pin.
4OTWR0h Indicates overtemperature warning.
3OTSDR0h Indicates overtemperature shutdown
2WD_FLTR0h Indicates watchdog timer fault.
1ITRIPR0h Indicates ITRIP regulation warning when any OUTx entered ITRIP.
0PVDD_OV_28VR0h Indicates overvoltage fault on PVDD pin greater than 28 V.

8.1.2 IC_STAT2 Register (Offset = 1h) [Reset = 0000h]

IC_STAT2 is shown in Table 8-6.

Return to the Summary Table.

Second device status register with SPI faults and specific thermal cluster fault/warning status.

Table 8-6 IC_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
15DEVICE_ERRR0h Indicates device OTP memory error has occurred.
14RESERVEDR0h Reserved
13SCLK_FLTR0h Indicates SPI clock (frame) fault when the number of SCLK pulses in a transaction frame are not equal to 24 bits, 1 byte address and two bytes data. Reported on bit SPI_ERR.
12RESERVEDR0h Reserved
11ZONE4_OTSDR0h Indicates overtemperature shutdown has occurred in zone 4.
10ZONE3_OTSDR0h Indicates overtemperature shutdown has occurred in zone 3.
9ZONE2_OTSDR0h Indicates overtemperature shutdown has occurred in zone 2.
8ZONE1_OTSDR0h Indicates overtemperature shutdown has occurred in zone 1.
7ZONE4_OTW_HR0h Indicates high temperature warning (above 145°C) has occurred in zone 4.
6ZONE3_OTW_HR0h Indicates high temperature warning (above 145°C) has occurred in zone 3.
5ZONE2_OTW_HR0h Indicates high temperature warning (above 145°C) has occurred in zone 2.
4ZONE1_OTW_HR0h Indicates high temperature warning (above 145°C) has occurred in zone 1.
3ZONE4_OTW_LR0h Indicates low temperature warning (above 125°C) has occurred in zone 4.
2ZONE3_OTW_LR0h Indicates low temperature warning (above 125°C) has occurred in zone 3.
1ZONE2_OTW_LR0h Indicates low temperature warning (above 125°C) has occurred in zone 2.
0ZONE1_OTW_LR0h Indicates low temperature warning (above 125°C) has occurred in zone 1.

8.1.3 GD_STAT Register (Offset = 2h) [Reset = 0000h]

GD_STAT is shown in Table 8-7.

Return to the Summary Table.

Gate driver status register with all gate driver faults and warnings, including smart gate driver faults and warnings.

Table 8-7 GD_STAT Register Field Descriptions
BitFieldTypeResetDescription
15DRVOFF_STAT_FBR0h DRVOFF analog latched status for gate driver. User can clear status bit after releasing DRVOFF pin and issuing CLR_FLT command.
14DRVOFF_STATR0h Indicates the latched status (high or low) of DRVOFF pin.
If DRVOFF pin is asserted, DRVOFF_STAT = 1b.
If DRVOFF pin is de-asserted, DRVOFF_STAT = 0b.
13STC_WARN_RR0h Indicates rising slew time TDRV overflow for gate driver half-bridge 1 and 2.
12STC_WARN_FR0h Indicates falling slew time TDRV overflow for gate driver half-bridge 1 and 2.
11PCHR_WARNR0h Indicates pre-charge underflow or overflow fault for gate driver half-bridge 1 and 2.
10PDCHR_WARNR0h Indicates pre-discharge underflow or overflow fault for gate driver half-bridge 1 and 2.
9IDIRR0h Indicates current direction for gate driver half-bridge 1 and 2.
8IDIR_WARNR0h Indicates unknown current direction for gate driver half-bridge 1 and 2
7VGS_L2R0h Indicates VGS gate fault on the low-side 2 MOSFET.
6VGS_H2R0h Indicates VGS gate fault on the high-side 2 MOSFET.
5VGS_L1R0h Indicates VGS gate fault on the low-side 1 MOSFET.
4VGS_H1R0h Indicates VGS gate fault on the high-side 1 MOSFET.
3VDS_L2R0h Indicates VDS overcurrent fault on the low-side 2 MOSFET.
2VDS_H2R0h Indicates VDS overcurrent fault on the high-side 2 MOSFET.
1VDS_L1R0h Indicates VDS overcurrent fault on the low-side 1 MOSFET.
0VDS_H1R0h Indicates VDS overcurrent fault on the high-side 1 MOSFET.

8.1.4 HB_STAT1 Register (Offset = 3h) [Reset = 0000h]

HB_STAT1 is shown in Table 8-8.

Return to the Summary Table.

Half-bridge overcurrent faults for either high- or low-side of each half-bridge.

Table 8-8 HB_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13OUT6_LS_OCPR0h Indicates overcurrent fault on low-side of half-bridge OUT6.
12OUT5_LS_OCPR0h Indicates overcurrent fault on low-side of half-bridge OUT5.
11OUT4_LS_OCPR0h Indicates overcurrent fault on low-side of half-bridge OUT4.
10OUT3_LS_OCPR0h Indicates overcurrent fault on low-side of half-bridge OUT3.
9OUT2_LS_OCPR0h Indicates overcurrent fault on low-side of half-bridge OUT2.
8OUT1_LS_OCPR0h Indicates overcurrent fault on low-side of half-bridge OUT1.
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5OUT6_HS_OCPR0h Indicates overcurrent fault on high-side of half-bridge OUT6.
4OUT5_HS_OCPR0h Indicates overcurrent fault on high-side of half-bridge OUT5.
3OUT4_HS_OCPR0h Indicates overcurrent fault on high-side of half-bridge OUT4.
2OUT3_HS_OCPR0h Indicates overcurrent fault on high-side of half-bridge OUT3.
1OUT2_HS_OCPR0h Indicates overcurrent fault on high-side of half-bridge OUT2.
0OUT1_HS_OCPR0h Indicates overcurrent fault on high-side of half-bridge OUT1.

8.1.5 HB_STAT2 Register (Offset = 4h) [Reset = 0000h]

HB_STAT2 is shown in Table 8-9.

Return to the Summary Table.

Half-bridge active and off-state open load faults.

Table 8-9 HB_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13RESERVEDR0h Reserved
12HB_OLP_STATR0h Indicates integrated half-bridge OLP status.
11OUT6_LS_OLAR0h Indicates active open load fault on low-side of half-bridge OUT6.
10OUT5_LS_OLAR0h Indicates active open load fault on low-side of half-bridge OUT5.
9OUT4_LS_OLAR0h Indicates active open load fault on low-side of half-bridge OUT4.
8OUT3_LS_OLAR0h Indicates active open load fault on low-side of half-bridge OUT3.
7OUT2_LS_OLAR0h Indicates active open load fault on low-side of half-bridge OUT2.
6OUT1_LS_OLAR0h Indicates active open load fault on low-side of half-bridge OUT1.
5OUT6_HS_OLAR0h Indicates active open load fault on high-side of half-bridge OUT6.
4OUT5_HS_OLAR0h Indicates active open load fault on high-side of half-bridge OUT5.
3OUT4_HS_OLAR0h Indicates active open load fault on high-side of half-bridge OUT4.
2OUT3_HS_OLAR0h Indicates active open load fault on high-side of half-bridge OUT3.
1OUT2_HS_OLAR0h Indicates active open load fault on high-side of half-bridge OUT2.
0OUT1_HS_OLAR0h Indicates active open load fault on high-side of half-bridge OUT1.

8.1.6 ITRIP_STAT Register (Offset = 5h) [Reset = 0000h]

ITRIP_STAT is shown in Table 8-10.

Return to the Summary Table.

Includes ITRIP regulation status warnings.

Table 8-10 ITRIP_STAT Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11RESERVEDR0h Reserved
10RESERVEDR0h Reserved
9RESERVEDR0h Reserved
8RESERVEDR0h Reserved
7RESERVEDR0h Reserved
6OUT7_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT7.
5OUT6_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT6.
4OUT5_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT5.
3OUT4_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT4.
2OUT3_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT3.
1OUT2_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT2.
0OUT1_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT1.

8.1.7 HS_STAT Register (Offset = 6h) [Reset = 0000h]

HS_STAT is shown in Table 8-11.

Return to the Summary Table.

High-side driver overcurrent and open load fault status.

Table 8-11 HS_STAT Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13OUT12_OLAR0h Indicates open load fault on OUT12.
12OUT11_OLAR0h Indicates open load fault on OUT11.
11OUT10_OLAR0h Indicates open load fault on OUT10.
10OUT9_OLAR0h Indicates open load fault on OUT9.
9OUT8_OLAR0h Indicates open load fault on OUT8.
8OUT7_OLAR0h Indicates open load fault on OUT7.
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5OUT12_OCPR0h Indicates overcurrent fault on OUT12.
4OUT11_OCPR0h Indicates overcurrent fault on OUT11.
3OUT10_OCPR0h Indicates overcurrent fault on OUT10.
2OUT9_OCPR0h Indicates overcurrent fault on OUT9.
1OUT8_OCPR0h Indicates overcurrent fault on OUT8.
0OUT7_OCPR0h Indicates overcurrent fault on OUT7.

8.1.8 HS_ITRIP_STAT Register (Offset = 7h) [Reset = 0000h]

HS_ITRIP_STAT is shown in Table 8-12.

Return to the Summary Table.

Includes High-side ITRIP status register.

Table 8-12 HS_ITRIP_STAT Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11RESERVEDR0h Reserved
10RESERVEDR0h Reserved
9RESERVEDR0h Reserved
8RESERVEDR0h Reserved
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5RESERVEDR0h Reserved
4OUT12_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT12.
3OUT11_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT11.
2OUT10_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT10.
1OUT9_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT9.
0OUT8_ITRIP_STATR0h Indicates ITRIP regulation warning on OUT8.

8.1.9 SPARE_STAT2 Register (Offset = 8h) [Reset = 0000h]

SPARE_STAT2 is shown in Table 8-13.

Return to the Summary Table.

Spare status register.

Table 8-13 SPARE_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11RESERVEDR0h Reserved
10RESERVEDR0h Reserved
9RESERVEDR0h Reserved
8RESERVEDR0h Reserved
7-0DEV_IDR0h 0x02= DRV8000
0x21= DRV8001
0x22= DRV8002