SLVSHE0 August   2025 DRV8002-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 High-Side Drivers
        1. 7.4.1.1 High-side Driver Control
          1. 7.4.1.1.1 High-side Driver PWM Generator
          2. 7.4.1.1.2 Constant Current Mode
          3. 7.4.1.1.3 OUTx HS ITRIP Behavior
          4. 7.4.1.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.1.2 High-side Driver Protection Circuits
          1. 7.4.1.2.1 High-side Drivers Internal Diode
          2. 7.4.1.2.2 High-side Driver Short-circuit Protection
          3. 7.4.1.2.3 High-side Driver Overcurrent Protection
          4. 7.4.1.2.4 High-side Driver Open Load Detection
      2. 7.4.2 Half-bridge Drivers
        1. 7.4.2.1 Half-bridge Control
        2. 7.4.2.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.2.3 Half-bridge Register Control
        4. 7.4.2.4 Half-Bridge ITRIP Regulation
        5. 7.4.2.5 Half-bridge Protection and Diagnostics
          1. 7.4.2.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.2.5.2 Half-bridge Open Load Detection
          3. 7.4.2.5.3 Half-Bridge Overcurrent Protection
      3. 7.4.3 Gate Drivers
        1. 7.4.3.1 Input PWM Modes
          1. 7.4.3.1.1 Half-Bridge Control
          2. 7.4.3.1.2 H-Bridge Control
          3. 7.4.3.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.3.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.3.2.1  Smart Gate Driver
          2. 7.4.3.2.2  Functional Block Diagram
          3. 7.4.3.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.3.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.3.2.4.1 tDRIVE Calculation Example
          5. 7.4.3.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.3.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
          7. 7.4.3.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.3.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.3.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.3.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.3.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.3.2.10.1 STC Control Loop Setup
        3. 7.4.3.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.3.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.3.5 Gate Driver Protection Circuits
          1. 7.4.3.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.3.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.3.5.3 Offline Short-circuit and Open Load Detection (OOL and OSC)
      4. 7.4.4 Sense Output (IPROPI)
      5. 7.4.5 Protection Circuits
        1. 7.4.5.1 Fault Reset (CLR_FLT)
        2. 7.4.5.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.5.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.5.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.5.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.5.6 Thermal Clusters
        7. 7.4.5.7 Watchdog Timer
        8. 7.4.5.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8002-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IDRIVE Calculation Example
        2. 9.2.2.2 tDRIVE Calculation Example
        3. 9.2.2.3 Maximum PWM Switching Frequency
        4. 9.2.2.4 Current Shunt Amplifier Configuration
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Pre-Production Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Device Comparison

Table 4-1 Device Comparison
Device Name H-Bridge Gate Driver Half-bridge Driver High-side Driver Lamp/LED HS Driver EC Gate Driver Heater HS Gate Driver Current Shunt Amp Package
DRV8000-Q1 1x 6x 5x 1x 1x 1x 1x 7x7 QFN-48 Wettable Flank
DRV8001-Q1 X 6x 5x 1x 1x 1x X 6x6 QFN-40 Wettable Flank
DRV8002-Q1 1x 6x 5x 1x

X

X

 1x 7x7 QFN-48 Wettable Flank
Table 4-2 Device Orderable Information
Device Pre-production Part Number Orderable Part Number EVM
DRV8000-Q1 PDRV8000QWRGZRQ1 DRV8000QWRGZRQ1 DRV8000-Q1EVM
P2DRV8000QWRGZRQ1
DRV8001-Q1 PDRV8001QWRHARQ1 DRV8001QWRHARQ1 DRV8001-Q1EVM
DRV8002-Q1 PDRV8002QRGZRQ1 DRV8002QWRGZRQ1 DRV8000-Q1EVM
P2DRV8002QWRGZRQ1