SLVSGZ1C May   2024  – February 2025 DRV8161 , DRV8162

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Bulk Capacitance Sizing
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
    8. 9.8 Community Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Layout Guidelines

  • Minimize length and impedance of GH, SH, GL, and SL traces. Use as few vias as possible to minimize parasitic inductance. The recommendation is to increase these trace widths shortly after routing away from the device pin to minimize parasitic resistance.
  • Keep bootstrap capacitor CBST close to the corresponding pins
  • Keep GVDD capacitors close to GVDD pin
  • Keep VDRAIN capacitor close to VDRAIN pin to supply steady switching current for the charge pump.
  • Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk capacitance is placed such that the bulk capacitance minimizes the length of any high current paths through the external MOSFETs. The connecting metal traces are as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and let the bulk capacitor deliver high current.
  • Connect SL pin to MOSFET source, not directly to GND, for accurate VDS detection.
  • DRV8161 only: Route SN/SP pins in parallel from the sense resistor to the device. Place filtering components close to the device pins to minimize post-filter noise coupling. Make sure that SN/SP stay separated from GND plane to achieve best CSA accuracy. The bypass capacitor across CSAREF and GND is placed closer to the device pin.
  • The hardware interface resistors RIDRIVE1, RIDRIVE2, RVDSLVL, RDTMODE, and RCSAGAIN are placed as close as possible to the device pins.
  • Minimize parallel routing to reduce noise coupling from potential noise source into any noise-sensitive device signals. The noise-sensitive signals include the multilevel hardware interface pins IDRIVE1, IDRIVE2, VDSLVL, DTMODE and CSAGAIN as well as the current sense amplifier output SO.

    DRV8161 DRV8162 DRV8161 Layout

    Figure 8-3 DRV8161 Layout