SLVSGZ1C May   2024  – February 2025 DRV8161 , DRV8162

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Bulk Capacitance Sizing
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
    8. 9.8 Community Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2.6 Multi-level digital input DT/MODE

Figure 7-14 shows the structure of mutlelevel input pin DT/MODE for hardware interface configuration. The input can be set with an external resistor RDTMODE connected to GND. The CDTMODE is optional to help reduce the impact of GND noise. The shoot through function, dead time insertion, and PWM control mode are configured as shown in Table 7-6. The information of LEVEL0, 1, 2, 3, and LEVEL5 are latched at the device power up.

DRV8161 DRV8162 DT/MODE Pin Structure Figure 7-14 DT/MODE Pin Structure
Table 7-6 DT/MODE Table
DT/MODE (RDTMODE) Shoot Through protection Dead Time Insertion (tDEAD) PWM Control mode
LEVEL5 (pin floating, >3.3MΩ) enabled disabled. tMINDEAD_VG is inserted when VGS dead time insertion is enabled via IDRIVE 2-pin PWM
LEVEL4 - Linear (10KΩ - 1MΩ) enabled enabled (20ns to 900ns) 1-pin PWM
LEVEL3 (3.3KΩ) enabled enabled (370ns) 2-pin PWM
LEVEL2 (1.3KΩ) enabled enabled (100ns) 2-pin PWM
LEVEL1 (470Ω) enabled enabled (20ns) 2-pin PWM
LEVEL0 (short to GND) disabled disabled Independent PWM

Use Equation 1 to calculate dead time in LEVEL4.

Equation 1. t d e a d ( n s ) = 0.89 × R D T M O D E ( k Ω ) + 11.1