SLVSFG5C September   2020  – February 2021 DRV8300

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 Gate Drive Timings
          1. 8.3.1.1.1 Propagation Delay
          2. 8.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 8.3.1.2 Mode (Inverting and non inverting INLx)
      2. 8.3.2 Pin Diagrams
      3. 8.3.3 Gate Driver Protective Circuits
        1. 8.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 8.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • 100-V Three Phase Half-Bridge Gate driver
    • Drives N-Channel MOSFETs (NMOS)
    • Gate Driver Supply (GVDD): 5-20V
    • MOSFET supply (SHx) support upto 100V
  • Integrated Bootstrap Diodes (DRV8300D devices)
  • Supports Inverting and Non-Inverting INLx inputs
  • Bootstrap gate drive architecture
    • 750-mA source current
    • 1.5-A sink current
  • Supports upto 15s battery powered applications
  • Low leakage current on SHx pins (<55 µA)
  • Absolute maximum BSTx voltage upto 115-V
  • Supports negative transients upto -22-V on SHx
  • Built-in cross conduction prevention
  • Adjustable deadtime through DT pin for QFN package variants
  • Fixed deadtime insertion of 200 nS for TSSOP package variants
  • Supports 3.3-V and 5-V logic inputs with 20V Abs max
  • 4 nS typical propogation delay matching
  • Compact QFN and TSSOP packages
  • Efficient system design with Power Blocks
  • Integrated protection features
    • BST undervoltage lockout (BSTUV)
    • GVDD undervoltage (GVDDUV)