SLVSFG5D September   2020  – March 2022 DRV8300

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 Gate Drive Timings
          1. 8.3.1.1.1 Propagation Delay
          2. 8.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 8.3.1.2 Mode (Inverting and non inverting INLx)
      2. 8.3.2 Pin Diagrams
      3. 8.3.3 Gate Driver Protective Circuits
        1. 8.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 8.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

DRV8300 is 100-V three half-bridge gate drivers, capable of driving high-side and low-side N-channel power MOSFETs. The DRV8300D generates the correct gate drive voltages using an integrated bootstrap diode and external capacitor for the high-side MOSFETs. The DRV8300N generates the correct gate drive voltages using an external bootstrap diode and external capacitor for the high-side MOSFETs. GVDD is used to generate gate drive voltage for the low-side MOSFETs. The Gate Drive architecture supports peak up to 750-mA source and 1.5-A sink currents.

The phase pins SHx is able to tolerate the significant negative voltage transients; while high side gate driver supply BSTx and GHx is able to support to higher positive voltage transients (125-V) abs max voltage which improves robustness of the system. Small propagation delay and delay matching specifications minimize the dead-time requirement which further improves efficiency. Undervoltage protection is provided for both low and high side through GVDD and BST undervoltage lockout.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DRV8300DIPW TSSOP (20) 6.40 mm × 4.40 mm
DRV8300DPW TSSOP (20) 6.40 mm × 4.40 mm
DRV8300NIPW TSSOP (20) 6.40 mm × 4.40 mm
DRV8300NPW TSSOP (20) 6.40 mm × 4.40 mm
DRV8300DRGE VQFN (24) 4.00 mm × 4.00 mm
DRV8300NRGE VQFN (24) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-F3087F4D-87E5-4BA8-A2BB-98BBC9C4E1CB-low.gifSimplified Schematic for DRV8300D
GUID-74442FEB-A062-4F10-BE5A-BE08B2B56EBD-low.gifSimplified Schematic for DRV8300N