If at any time the input supply voltage on the VM pin falls below the VVM_UV threshold or voltage on VDRAIN pin falls below the VVDR_UV, all of the external MOSFETs are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and UVLO bits are also latched high in the registers on SPI devices. Normal operation continues (gate driver operation and the nFAULT pin is released) when the undervoltage condition is removed. The UVLO bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).
VM supply or VDRAIN undervoltage may also lead to VCP charge pump or VGLS regulator undervoltage conditions to report. This behavior is expected because the VCP and VGLS supply voltages are dependent on VM and VDRAIN pin voltages.