SLVSFF0B June   2020  – July 2022 DRV8436E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
    1.     Device Options
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Bridge Control
      3. 7.3.3 Current Regulation
      4. 7.3.4 Decay Modes
        1. 7.3.4.1 Slow Decay
        2. 7.3.4.2 Mixed Decay
        3. 7.3.4.3 Fast Decay
        4. 7.3.4.4 Smart tune Dynamic Decay
        5. 7.3.4.5 Blanking time
      5. 7.3.5 Charge Pump
      6. 7.3.6 Linear Voltage Regulators
      7. 7.3.7 Logic and Quad-Level Pin Diagrams
        1. 7.3.7.1 nFAULT Pin
      8. 7.3.8 Protection Circuits
        1. 7.3.8.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.8.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.8.3 Overcurrent Protection (OCP)
        4. 7.3.8.4 Thermal Shutdown (OTSD)
        5. 7.3.8.5 36
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Primary Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Current Regulation
        2. 8.3.2.2 Stepper Motor Speed
        3. 8.3.2.3 Decay Modes
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, DVDD)
IVM VM operating supply current nSLEEP = 1, No motor load, IC Enabled 5

7

 mA
IVMQ VM sleep mode supply current nSLEEP = 0 2 4 μA
tSLEEP Sleep time nSLEEP = 0 to sleep-mode 75 μs
tWAKE Wake-up time nSLEEP = 1 to output transition 0.6 0.9 ms
tON Turn-on time VM > UVLO to output transition 0.6 0.9 ms
VDVDD Internal regulator voltage No external load, 6 V < VVM < 45 V 4.5 5 5.5 V
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage VVM + 5 V
f(VCP) Charge pump switching frequency VVM > UVLO; nSLEEP = 1 400 kHz
LOGIC-LEVEL INPUTS (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2, nSLEEP)
VIL Input logic-low voltage 0 0.6 V
VIH Input logic-high voltage 1.5 5.5 V
VHYS Input logic hysteresis 150 mV
IIL Input logic-low current VIN = 0 V –1 1 μA
IIH Input logic-high current VIN = 5 V 50 μA
tPD Propagation delay xPH, xEN, xINx input to current change 850 ns
QUAD-LEVEL INPUTS (ADECAY, BDECAY, TOFF)
VI1 Input logic-low voltage Tied to GND 0 0.6 V
VI2 330kΩ ± 5% to GND 1 1.25 1.4 V
VI3 Input Hi-Z voltage Hi-Z (>500kΩ to GND) 1.8 2 2.2 V
VI4 Input logic-high voltage Tied to DVDD 2.7 5.5 V
IO Output pull-up current 10 μA
CONTROL OUTPUTS (nFAULT)
VOL Output logic-low voltage IO = 5 mA 0.4 V
IOH Output logic-high leakage VVM = 24 V –1 1 μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ON) High-side FET on resistance VVM = 24 V, TJ = 25°C, IO = -1 A 450 550 mΩ
VVM = 24 V, TJ = 125°C, IO = -1 A 700 850 mΩ
VVM = 24 V, TJ = 150°C, IO = -1 A 780 950 mΩ
RDS(ON) Low-side FET on resistance VVM = 24 V, TJ = 25°C, IO = 1 A 450 550 mΩ
VVM = 24 V, TJ = 125°C, IO = 1 A 700 850 mΩ
VVM = 24 V, TJ = 150°C, IO = 1 A 780 950 mΩ
tSR Output slew rate VM = 24V, IO = 0.5 A, Between 10% and 90% 150 V/µs
PWM CURRENT CONTROL (VREFA, VREFB)
KV Transimpedance gain 2.2 V/A
tOFF PWM off-time TOFF = 0 7 μs
TOFF = 1 16
TOFF = Hi-Z 24
TOFF = 330 kΩ to GND 32
ΔITRIP Current trip accuracy IO = 1.5 A, 10% to 20% current setting –13 10 %
IO = 1.5 A, 20% to 67% current setting –8 8
IO = 1.5 A, 67% to 100% current setting –7.5 7.5
IO,CH AOUT and BOUT current matching IO = 1.5 A –2.5 2.5 %
PROTECTION CIRCUITS
VUVLO VM UVLO lockout VM falling, UVLO falling 4.15 4.25 4.35 V
VM rising, UVLO rising 4.25 4.35 4.45
VUVLO,HYS Undervoltage hysteresis Rising to falling threshold 100 mV
VCPUV Charge pump undervoltage VCP falling; CPUV report VVM + 2 V
IOCP Overcurrent protection Current through any FET 2.4 A
tOCP Overcurrent deglitch time VM < 37V 3 μs
VM >= 37V 0.5
tRETRY Overcurrent retry time 4 ms
TOTSD Thermal shutdown Die temperature TJ 150 165 180 °C
THYS_OTSD Thermal shutdown hysteresis Die temperature TJ 20 °C