SLVSC40H June   2013  – May 2020 DRV8711

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Indexer Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Decay Modes
      6. 7.3.6  Blanking Time
      7. 7.3.7  Predrivers
      8. 7.3.8  Configuring Predrivers
      9. 7.3.9  External FET Selection
      10. 7.3.10 Stall Detection
        1. 7.3.10.1 Internal Stall Detection
        2. 7.3.10.2 External Stall Detection
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 Overcurrent Protection (OCP)
        2. 7.3.11.2 Predriver Fault
        3. 7.3.11.3 Thermal Shutdown (TSD)
        4. 7.3.11.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET and SLEEPn Operation
      2. 7.4.2 Microstepping Drive Current
    5. 7.5 Programming
      1. 7.5.1 Serial Data Format
    6. 7.6 Register Maps
      1. 7.6.1 Control Registers
      2. 7.6.2 CTRL Register (Address = 0x00)
      3. 7.6.3 TORQUE Register (Address = 0x01)
      4. 7.6.4 OFF Register (Address = 0x02)
      5. 7.6.5 BLANK Register (Address = 0x03)
      6. 7.6.6 DECAY Register (Address = 0x04)
      7. 7.6.7 STALL Register (Address = 0x05)
      8. 7.6.8 DRIVE Register (Address = 0x06)
      9. 7.6.9 STATUS Register (Address = 0x07)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sense Resistor
      2. 8.1.2 Optional Series Gate Resistor
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Set Step Rate
        2. 8.2.2.2 Calculate Current Regulation
        3. 8.2.2.3 Support External FETs
        4. 8.2.2.4 Pick Decay Mode
        5. 8.2.2.5 Config Stall Detection
        6. 8.2.2.6 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current VM = 24 V 17 20 mA
IVMQ VM sleep mode supply current VM = 24 V, SLEEPn = 0, TA = 25°C 65 98 μA
VUVLO VM undervoltage lockout voltage VM rising 7.1 8 V
VM falling 6.3
INTERNAL LINEAR REGULATORS
V5 V5 output voltage VM ≥ 12 V, IOUT = 1 mA – 10 mA 4.8 5 5.2 V
VINT VINT voltage No external load – reference only 1.7 1.8 1.9 V
LOGIC-LEVEL INPUTS
VIL Input low voltage 0.8 V
VIH Input high voltage 1.5 V
VHYS Input hysteresis voltage 300 mV
IIL Input low current VIN = 0 V –5 5 μA
IIH Input high current VIN = 5 V 30 50 70 μA
SDATAO, STALLn, FAULTn OUTPUTS (OPEN-DRAIN OUTPUTS)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 µA
MOSFET DRIVERS
VOUTH High-side gate drive output voltage VM = 24 V, IO = 100 μA VM+10 V
VOUTL Low-side gate drive output voltage VM = 24 V, IO = 100 μA 10 V
tDEAD Output dead time digital delay (dead time is enforced in analog circuits) DTIME = 00 400 ns
DTIME = 01 450
DTIME = 10 650
DTIME = 11 850
IOUTH Peak output current gate drive (source) IDRIVEP = 00 50 mA
IDRIVEP = 01 100
IDRIVEP = 10 150
IDRIVEP = 11 200
IOUTl Peak output current gate drive (sink) IDRIVEN = 00 100 mA
IDRIVEN = 01 150
IDRIVEN = 10 200
IDRIVEN = 11 400
tDRIVE Peak current drive time (source) TDRIVEP = 00 250 ns
TDRIVEP = 01 500
TDRIVEP = 10 1000
TDRIVEP = 11 2000
tDRIVE Peak current drive time (sink) TDRIVEN = 00 250 ns
TDRIVEN = 01 500
TDRIVEN = 10 1000
TDRIVEN = 11 2000
MOTOR DRIVER
tOFF PWM off time adjustment range Set by TOFF register 0.5 128 μs
tBLANK Current sense blanking time Set by TBLANK register 0.5 5.12 μs
PROTECTION CIRCUITS
VOCP Overcurrent protection trip level (Voltage drop across external FET) OCPTH = 00 160 250 320 mV
OCPTH = 01 380 500 580
OCPTH = 10 620 750 850
OCPTH = 11 840 1000 1200
tTSD Thermal shutdown temperature(1) Die temperature 150 160 180 °C
tHYS Thermal shutdown hysteresis 20 °C
CURRENT SENSE AMPLIFIERS
AV Gain ISGAIN = 00 5 V/V
ISGAIN = 01 10
ISGAIN = 10 20
ISGAIN = 11 40
tSET Settling time (to ±1%) ISGAIN = 00, ΔVIN = 400 mV 150 ns
ISGAIN = 01, ΔVIN = 200 mV 300
ISGAIN = 10, ΔVIN = 100 mV 600
ISGAIN = 11, ΔVIN = 50 mV 1.2 µs
VOFS Offset voltage ISGAIN = 00, input shorted 4 mV
VIN Input differential voltage range –600 600 mV
CURRENT CONTROL DACs
Resolution 256 steps
Full-scale step response 10% to 90% 5 µs
VREF Full-scale (reference) voltage 2.50 2.75 3 V
(1) Not tested in production; ensured by design.