10.1 Layout Guidelines

The VMA and VMB pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1 μF rated for VM. This capacitor should be placed as close to the VMA and VMB pins as possible with a thick trace or ground plane connection to the device GND pin.

The VMA and VMB pins must be bypassed to ground using an appropriate bulk capacitor. This component may be an electrolytic and should be located close to the DRV8811 device.

A low-ESR ceramic capacitor must be placed between the CP1 and CP2 pins. TI recommends a value of 0.22 μF rated for VM. Place this component as close to the pins as possible.

A low-ESR ceramic capacitor must be placed between the VM and VCP pins. TI recommends a value of 0.22 μF rated for 16 V. Place this component as close to the pins as possible.

Ensure proper connection of the DRV8811 thermal pad to the PCB. The thermal pad should be connected to a copper plane that is connected to GND. The copper plane should have a large area to allow for thermal dissipation from the DRV8811 device.

10.2 Layout Example

Figure 14. Layout Example Schematic

10.3 Thermal Information

The DRV8811 device has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature exceeds approximately 150°C, the device is disabled until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature.

10.3.1 Heatsinking

The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.

For details about how to design the PCB, see TI Application Report SLMA002, PowerPAD™ Thermally Enhanced Package and TI Application Brief SLMA004, PowerPAD™ Made Easy, available at www.ti.com.

In general, the more copper area that can be provided, the more power can be dissipated. Figure 18 shows thermal resistance vs copper plane area for a single-sided PCB with 2-oz. copper heatsink area. It can be seen that the heatsink effectiveness increases rapidly to about 20 cm², then levels off somewhat for larger areas.

Figure 15. Power Dissipation
(2-Layer)

Figure 17. Typical r_DS(on)
vs
Temperature

Figure 16. Power Dissipation
(4-Layer)

Figure 18. Thermal Resistance
vs
Copper Area

10.4 Power Dissipation

Power dissipation in the DRV8811 device is dominated by the power dissipated in the output FET resistance, or r_DS(on). Average power dissipation when running a stepper motor can be roughly estimated by:

Equation 8.

where P_TOT is the total power dissipation, r_DS(on) is the resistance of each FET, and I_OUT(RMS) is the RMS output current being applied to each winding. I_OUT(RMS) is equal to the approximately 0.7× the full-scale output current setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are conducting winding current for each winding (one high-side and one low-side).

The maximum amount of power that can be dissipated in the DRV8811 device is dependent on ambient temperature and heatsinking. Figure 15 and Figure 16 show how the maximum allowable power dissipation varies according to temperature and PCB construction. Figure 15 shows data for a JEDEC 2-layer low-K board with 2-oz. copper, 76 mm × 114 mm × 1.6 mm thick, with either no backside copper or a 24 cm² copper area on the backside. Similarly, Figure 16 shows data for a JEDEC 4-layer high-K board with 1-oz. copper, 76 mm × 114 mm × 1.6 mm thick, and a solid internal ground plane. In this case, the thermal pad is tied to the ground plane using thermal vias, and no additional outer layer copper.

Note that r_DS(on) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. See Figure 17.