SLVSDS7B August 2019 – November 2019 DRV8876
Refer to the PDF data sheet for device specific package drawings
After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the nSLEEP pin is logic high, and tWAKE has elapsed, the device enters its active mode. In this mode, the H-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. The input control mode (PMODE) and current control modes (IMODE) will be latched when the device enters active mode.