SLVSDS7B August 2019 – November 2019 DRV8876
The DRV887x family of devices provides three modes to support different control schemes with the EN/IN1 and PH/IN2 pins. The control mode is selected through the PMODE pin with either logic low, logic high, or setting the pin Hi-Z as shown in Table 2. The PMODE pin state is latched when the device is enabled through the nSLEEP pin. The PMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time, changing the PMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high.
|PMODE STATE||CONTROL MODE|
|PMODE = Logic Low||PH/EN|
|PMODE = Logic High||PWM|
|PMODE = Hi-Z||Independent Half-Bridge|
The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive modes. The device input pins can be powered before VM is applied with no issues. By default, the EN/IN1 and PH/IN2 pins have an internal pulldown resistor to ensure the outputs are Hi-Z if no inputs are present.
The sections below show the truth table for each control mode. Note that these tables do not take into account the internal current regulation feature. Additionally, the DRV887x family of devices automatically handles the dead-time generation when switching between the high-side and low-side MOSFET of a half-bridge.
Figure 10 describes the naming and configuration for the various H-bridge states.