SNLS729 September   2025 DS160PR410-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Receiver Detect State Machine
      4. 6.3.4 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Linear Equalizer (Buffer) Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 x4 Lane Configuration
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.1.2 Detailed Design Procedure

In PCIe Gen 3.0, and 4.0 applications, the specification requires Rx-Tx (of root-complex and endpoint) link training to establish and optimize signal conditioning settings at 8Gbps and 16Gbps respectively. In link training, the Rx partner requests a series of FIR – preshoot and de-emphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes CTLE and DFE. The link training pre-conditions the signal, with an equalized link between the root-complex and endpoint resulting an optimized link. Note that there is no link training in PCIe Gen 1.0 (2.5Gbps) or PCIe Gen 2.0 (5.0Gbps) applications.

For operation in Gen 3.0, and 4.0 links, the DS160PR410-Q1 is designed with linear data-path to pass the Tx Preset signaling (by root complex and end point) onto the Rx (of root complex and end point) for the PCIe Gen 3.0, and 4.0 link to train and optimize the equalization settings. The linear redriver DS160PR410-Q1 helps extend the PCB trace reach distance by boosting the attenuated signals with its equalization, which allows the user to recover the signal by the link partner's Rx more easily. The device must be placed in between the Tx and Rx (of root complex and end point) in such a way that both Rx and Tx signal swings stay within the linearity range of the device. Adjustments to the DS160PR410-Q1 EQ setting should be performed based on the channel loss to optimize the eye opening in the Rx partner. The available EQ gain settings are provided in Table 6-1. For most PCIe systems the default flat gain setting 0.6dB (GAIN = floating) would be sufficient. However, a flat gain attenuation can be used to apply extra equalization when needed to keep the data-path linear.

The DS160PR410-Q1 can be optimized for a given system using the three configuration modes – Pin mode, SMBus/I2C Controller mode, and SMBus/I2C Target mode. In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7kΩ is a good first approximation for a bus capacitance of 10pF.

In PCIe applications PD pin can be connected to PCIe sideband signals PERST# with inverted polarity or one or more appropriate PRSNTx# signals to achieve desired RX detect functionality.

The DS160PR410-Q1 can be optimized for a given system using the three configuration modes – Pin mode, SMBus/I2C Controller mode, and SMBus/I2C Target mode. In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7kΩ is a good first approximation for a bus capacitance of 10pF.

Figure 7-3 shows a simplified schematic for x4 lane configuration in pin-strap, EEPROM and SMBus Target modes.

DS160PR410-Q1 Simplified Schematic for PCIe x4 Lane Configuration in Pin-strap, EEPROM and SMBus Target Modes Figure 7-3 Simplified Schematic for PCIe x4 Lane Configuration in Pin-strap, EEPROM and SMBus Target Modes