SNLS729 September   2025 DS160PR410-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Receiver Detect State Machine
      4. 6.3.4 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Linear Equalizer (Buffer) Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 x4 Lane Configuration
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3 Receiver Detect State Machine

The DS160PR410-Q1 deploys an Rx detect state machine that governs the Rx detection cycle as defined in the PCI express specifications. At power up or after a manual PD or SEL toggle the redriver determines whether or not a valid PCI express termination is present at the far end receiver. The RX_DET pin of DS160PR410-Q1 provides additional flexibility for system designers to appropriately set the device in desired mode as provided in Table 6-3. For most applications the RX_DET pin can be left floating for default settings. In SMBus/I2C mode each channel can be configured independently.

Table 6-3 Receiver Detect State Machine Settings
PD RX_DET Rx Common-mode Impedance COMMENTS
L L0 Always 50Ω PCI Express Rx detection state machine is disabled. Recommended for non PCIe interface use case where the DS160PR410-Q1 is used as buffer with equalization.
L L1 Pre Detect: Hi-Z
Post Detect: 50Ω.		 Outputs polls until 3 consecutive valid detections
L L2 Pre Detect: Hi-Z
Post Detect: 50Ω.		 Outputs polls until 2 consecutive valid detections
L L3 NA Reserved
L L4 (Float) Pre Detect: Hi-Z
Post Detect: 50Ω.		 Tx polls every ≅150µs until valid termination is detected. Rx CM impedance held at Hi-Z until detection Reset by asserting PD high for 200µs then low.
H X Hi-Z Set their Rx impedance to Hi-Z

In PCIe applications PD pins can be connected to PCIe sideband signals PERST# with inverted polarity or one or more appropriate PRSNTx# signals to achieve desired RX detect functionality.