5 Pin Configuration and Functions

Figure 5-1 RHB Package
32-Pin VQFN
Top View

Table 5-1 Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
CSI INTERFACE
CSI_CLKP	5	I, DPHY	CSI-2 clock input pins. Connect to a CSI-2 clock source with matched 100-Ω (±5%) impedance interconnects.
CSI_CLKN	6	I, DPHY
CSI_D0P	3	I, DPHY	CSI-2 data input pins. Connect to a CSI-2 data sources with matched 100-Ω (±5%) impedance interconnects. If unused, these pins may be left floating.
CSI_D0N	4	I, DPHY
CSI_D1P	1	I, DPHY
CSI_D1N	2	I, DPHY
CSI_D2P	31	I, DPHY
CSI_D2N	32	I, DPHY
CSI_D3P	29	I, DPHY
CSI_D3N	30	I, DPHY
SERIAL CONTROL INTERFACE
I2C_SDA	23	OD	I2C Data and Clock Pins. Typically pulled up by 470-Ω to 4.7-kΩ resistors to either 1.8-V or 3.3-V supply rail depending on IDX setting. See I2C Interface Configuration for further details on the I2C implementation of the DS90UB935-Q1.
I2C_SCL	24	OD
CONFIGURATION and CONTROL
RES0	7	I	Reserved pin – Connect to GND
RES1	22	I	Reserved pin – Do not connect (leave floating)
PDB	8	I, PD	Power-down inverted Input Pin. Internal 1-MΩ pulldown. Typically connected to processor GPIO with pull down. When PDB input is brought HIGH, the device is enabled and internal register and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN. PDB should remain low until after power supplies are applied and reach minimum required levels. See Power Down (PDB) for further details on the function of PDB. PDB INPUT IS NOT 3.3-V TOLERANT. PDB = 1.8 V, device is enabled (normal operation) PDB = 0, device is powered down.
MODE	21	I, S	Mode select configuration input. Default operational mode will be strapped at start-up based on the MODE input voltage when PDB transitions LOW to HIGH. Typically connected to voltage divider through external pullup to VDD18 and pulldown to GND applying an appropriate bias voltage. See MODE for details.
CLK_OUT/IDX	19	I/O, S	IDX pin sets the I2C pullup voltage and device address; connect to external pullup to VDD and pulldown to GND to create a voltage divider. When PDB transitions LOW to HIGH, the strap input voltage is sensed at the CLOCK_OUT/IDX pin to determine functionality and then converted to CLK_OUT. See I2C Interface Configuration for details. If CLK_OUT is used, the minimum resistance on the pin is 35 kΩ. If unused, CLK_OUT/IDX may be tied to GND.
FPD-LINK III INTERFACE
DOUT-	13	I/O	FPD-Link III Input/Output pins. These pins must be AC-coupled. See Figure 8-5 and Figure 8-6 for typical connection diagrams and Table 8-3 for recommended capacitor values.
DOUT+	14	I/O
POWER AND GROUND
VDDD_CAP	26	D, P	A connection for an internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details.
VDDDRV_CAP	15	D, P	A connection for an internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details.
VDDPLL_CAP	10	D, P	A connection for an internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details.
VDDD	25	P	1.8-V (±5%) Power Supply pin. Typically connected to 1-µF and 0.01-µF capacitors to GND.
VDDDRV	16	P	1.8-V (±5%) Analog Power Supply pin. Typically connected to 1-µF and 0.01-µF capacitors to GND.
VDDPLL	11	P	1.8-V (±5%) Analog Power Supply pin. Typically connected to 1-µF and 0.01-µF capacitors to GND.
GND	DAP	G	DAP is the large metal contact at the bottom side, located at the center of the VQFN package. Connect to the ground plane (GND).
LOOP FILTER
LPF1	9	P	Loop Filter 1: Connect as described in Section 8.2.2.4.
LPF2	12	P	Loop Filter 2: Connect as described in Section 8.2.2.4.
CLOCK INTERFACE AND GPIO
GPIO_0	17	I/O, PD	General-Purpose Input/Output pins. These pins can also be configured to sense the voltage at their inputs. See Voltage and Temperature Sensing. At power up, these GPIO pins default to inputs with a 300-kΩ (typical) internal pulldown resistor. These pins may be left floating if unused, but TI recommends to set the GPIOx_INPUT_EN to 0 to disable the pins. See Section 7.3.6 for programmability.
GPIO_1	18	I/O, PD
GPIO_2	27	I/O, PD	General-Purpose Input/Output pins. At power up, these GPIO pins default to inputs with a 300-kΩ (typical) internal pulldown resistor. These pins may be left floating if unused, but TI recommends to set the GPIOx_INPUT_EN to 0 to disable the pins. See Section 7.3.6 for programmability.
GPIO_3	28	I/O. PD
CLKIN	20	I	Reference Clock Input pin. If operating in non-sync external clock mode, connect this pin to a local clock source. If unused (like other clocking modes), this pin may be left open. See Table 7-7 for more information on clocking modes.