SNOS521E January   2001  – January 2018 DS92LV040A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Functional Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuits and Timing Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Supply Voltage
        2. 9.2.3.2 Supply Bypass Capacitance
        3. 9.2.3.3 Termination Resistors
        4. 9.2.3.4 Interconnecting Media
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Application Information

The DS92LV040A is a Bus LVDS transceiver intended to be used in a differential backplane configuration. Transceivers or receivers are connected to the driver through a balanced media such as differential PCB traces. Typically, the characteristic differential impedance of the media (ZO) is in the range of 50 Ω to 100 Ω. Two termination resistors of ZO Ω each are placed at the ends of the transmission line backplane. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. The effects of mid-stream connector(s), cable stub(s), and other impedance discontinuity as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

The output current is typically 12 mA. The current mode requires that a resistive termination be employed to terminate the signal and to complete the loop. Unterminated configurations are not allowed. The 12 mA loop current will develop a differential voltage of about 300 mV across a 27 Ω (double terminated 54Ω differential transmission backplane) effective resistance, which the receiver detects with a 230 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (300 mV – 70 mV = 230 mV)). The signal is centered around +1.2 V (Driver Offset, VOS ) with respect to ground. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 600 mV.