SBOS938C October   2018  – June 2020 INA901-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Basic Connection
      2. 7.3.2 Selecting RS
      3. 7.3.3 Transient Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 First- or Second-Order Filtering
      2. 7.4.2 Accuracy Variations as a Result of VSENSE and Common-Mode Voltage
        1. 7.4.2.1 Normal Case 1: VSENSE ≥ 20 mV, VCM ≥ VS
        2. 7.4.2.2 Normal Case 2: VSENSE ≥ 20 mV, VCM < VS
        3. 7.4.2.3 Low VSENSE Case 1: VSENSE < 20 mV, –15 V ≤ VCM < 0; and Low VSENSE Case 3: VSENSE < 20 mV, VS < VCM ≤ 65 V
        4. 7.4.2.4 Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤ VCM ≤ VS
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 RFI and EMI
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VS = 2.7 V and 16 V, VCM = –15 V, 12 V and 65 V, VSENSE = 100 mV, and PRE OUT connected to BUF IN, unless otherwise noted. TA is as shown in SUBGROUP column.
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
INPUT
VSENSE Full-scale input voltage VSENSE = (VIN+) – (VIN–) [1, 2, 3] 0.15 (VS  – 0.2) / Gain V
VCM Common-mode input range [1, 2, 3] –15 65 V
CMRR Common-mode rejection ratio VIN+ = –15 V to 65 V [1] 80 120 dB
[2, 3] 70 120
VOS Offset voltage, RTI [1] ±0.5 ±2.5 mV
[2, 3] ±3.5
dVOS/dT 2.5 μV/°C
PSR VOS vs power-supply [1, 2, 3] 5 250 μV/V
IB Input bias current, VIN– pin [1] ±8 ±16 μA
[2, 3] ±19
PRE OUT output impedance 96 kΩ
Buffer input bias current –50 nA
Buffer input bias current temperature coefficient ±0.03 nA/°C
OUTPUT (VSENSE ≥ 20 mV)(3)
G Gain 20 V/V
GBUF Output buffer gain 2 V/V
Total gain error VSENSE = 20 mV to 100 mV [4, 5, 6] ±0.2% ±1.5%
Total gain error vs temperature TA = –55 °C to 125 °C 50 ppm/°C
Total output error(4) [4] ±0.75% ±2%
[5, 6] ±3%
Nonlinearity error VSENSE = 20 mV to 100 mV ±0.002%
RO Output impedance, pin 5 1.5 Ω
Maximum capacitive load No sustained oscillation 10 nF
VOLTAGE OUTPUT (RL = 10 kΩ to GND)
Swing to V+ power-supply rail [1, 2, 3] (V+) – 0.05 (V+) – 0.2 V
Swing to GND [1, 2, 3] VGND + 0.003 VGND + 0.05 V
FREQUENCY RESPONSE
BW Bandwidth CLOAD = 5 pF 130 kHz
Phase margin CLOAD < 10 nF 40 °
SR Slew rate 1 V/μs
tS Settling time (1%) VSENSE = 10 mV to 100 mVPP,
CLOAD = 5 pF		 2 μs
NOISE, RTI(2)
en Voltage noise density 40 nV/√Hz
POWER SUPPLY
VS Operating range [1, 2, 3] 2.7 16 V
IQ Quiescent current VOUT = 2 V [1] 700 900 μA
[2, 3] 700 1200
VSENSE = 0 mV [1] 350 500
[2, 3] 350 650
(1) For subgroup definitions, see the Quality Conformance Inspection table.
(2) RTI means Referred-to-Input.
(3) For output behavior when VSENSE < 20 mV, see the Accuracy Variations as a Result of VSENSE and Common-Mode Voltage section.
(4) Total output error includes effects of gain error and VOS.