SNOSDD0 December   2021 LDC3114

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Digital Interface
    7. 6.7 I2C Interface
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Multimode Operation
      2. 7.3.2 Multichannel and Single-Channel Operation
      3. 7.3.3 Raw Data Output
      4. 7.3.4 Button Output Interfaces
      5. 7.3.5 Programmable Button Sensitivity
      6. 7.3.6 Baseline Tracking
      7. 7.3.7 Integrated Button Algorithms
      8. 7.3.8 I2C Interface
        1. 7.3.8.1 I2C Interface Specifications
        2. 7.3.8.2 I2C Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Power Mode
      2. 7.4.2 Low Power Mode
      3. 7.4.3 Configuration Mode
    5. 7.5 Register Maps
      1. 7.5.1 LDC3114 Registers
      2. 7.5.2 Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Theory of Operation
      2. 8.1.2  Designing Sensor Parameters
      3. 8.1.3  Setting COM Pin Capacitor
      4. 8.1.4  Defining Power-On Timing
      5. 8.1.5  Configuring Button or Raw Data Scan Rate
      6. 8.1.6  Programming Button or Raw Data Sampling Window
      7. 8.1.7  Scaling Frequency Counter Output
      8. 8.1.8  Setting Button Triggering Threshold
      9. 8.1.9  Tracking Baseline
      10. 8.1.10 Mitigating False Button Detections
        1. 8.1.10.1 Eliminating Common-Mode Change (Anti-Common)
        2. 8.1.10.2 Resolving Simultaneous Button Presses (Max-Win)
        3. 8.1.10.3 Overcoming Case Twisting (Anti-Twist)
        4. 8.1.10.4 Mitigating Metal Deformation (Anti-Deform)
      11. 8.1.11 Reporting Interrupts for Button Presses, Raw Data Ready and Error Conditions
      12. 8.1.12 Estimating Supply Current
    2. 8.2 Typical Application
      1. 8.2.1 Touch Button Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1 LDC3114 Registers

#LDC3114_LDC3114_TABLE_1 lists the memory-mapped registers for the LDC3114 registers. All register offset addresses not listed in #LDC3114_LDC3114_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 LDC3114 Registers
Offset Acronym Register Name Section
0h STATUS Device status #LDC3114_LDC3114_LDC3114_STATUS
1h OUT Channel output logic states #LDC3114_LDC3114_LDC3114_OUT
2h DATA0_LSB The lower 8 bits of the Button 0 data (Two's complement #LDC3114_LDC3114_LDC3114_DATA0_LSB
3h DATA0_MSB The upper 4 bits of the Button 0 data (Two's complement) #LDC3114_LDC3114_LDC3114_DATA0_MSB
4h DATA1_LSB The lower 8 bits of the Button 1 data (Two's complement) #LDC3114_LDC3114_LDC3114_DATA1_LSB
5h DATA1_MSB The upper 4 bits of the Button 1 data (Two's complement) #LDC3114_LDC3114_LDC3114_DATA1_MSB
6h DATA2_LSB The lower 8 bits of the Button 2 data (Two's complement) #LDC3114_LDC3114_LDC3114_DATA2_LSB
7h DATA2_MSB The upper 4 bits of the Button 2 data (Two's complement) #LDC3114_LDC3114_LDC3114_DATA2_MSB
8h DATA3_LSB The lower 8 bits of the Button 3 data (Two's complement) #LDC3114_LDC3114_LDC3114_DATA3_LSB
9h DATA3_MSB The upper 4 bits of the Button 3 data (Two's complement) #LDC3114_LDC3114_LDC3114_DATA3_MSB
Ah RESET Reset device and register configurations #LDC3114_LDC3114_LDC3114_RESET
Ch EN Enable channels and low power modes #LDC3114_LDC3114_LDC3114_EN
Dh NP_SCAN_RATE Normal Power Mode scan rate #LDC3114_LDC3114_LDC3114_NP_SCAN_RATE
Eh GAIN0 Gain for Channel 0 sensitivity adjustment for button algorithm #LDC3114_LDC3114_LDC3114_GAIN0
Fh LP_SCAN_RATE Low Power Mode scan rate #LDC3114_LDC3114_LDC3114_LP_SCAN_RATE
10h GAIN1 Gain for Channel 1 sensitivity adjustment for button algorithm #LDC3114_LDC3114_LDC3114_GAIN1
11h INTPOL Interrupt polarity #LDC3114_LDC3114_LDC3114_INTPOL
12h GAIN2 Gain for Channel 2 sensitivity adjustment for button algorithm #LDC3114_LDC3114_LDC3114_GAIN2
13h LP_BASE_INC Low power base increment for button algorithm #LDC3114_LDC3114_LDC3114_LP_BASE_INC
14h GAIN3 Gain for Channel 3 sensitivity adjustment for button algorithm #LDC3114_LDC3114_LDC3114_GAIN3
15h NP_BASE_INC Normal power base increment for button algorithm #LDC3114_LDC3114_LDC3114_NP_BASE_INC
16h BTPAUSE_MAXWIN Baseline tracking pause and Max-win for button algorithm #LDC3114_LDC3114_LDC3114_BTPAUSE_MAXWIN
17h LC_DIVIDER LC oscillation frequency divider #LDC3114_LDC3114_LDC3114_LC_DIVIDER
18h HYST Hysteresis for threshold for button algorithm #LDC3114_LDC3114_LDC3114_HYST
19h TWIST Anti-twist for button algorithm #LDC3114_LDC3114_LDC3114_TWIST
1Ah COMMON_DEFORM Anti-common and anti-deformation for button algorithm #LDC3114_LDC3114_LDC3114_COMMON_DEFORM
1Ch OPOL_DPOL Output polarity for button data and output #LDC3114_LDC3114_LDC3114_OPOL_DPOL
1Eh CNTSC Counter scale #LDC3114_LDC3114_LDC3114_CNTSC
20h SENSOR0_CONFIG Sensor 0 cycle count, frequency, RP range #LDC3114_LDC3114_LDC3114_SENSOR0_CONFIG
22h SENSOR1_CONFIG Sensor 1 cycle count, frequency, RP range #LDC3114_LDC3114_LDC3114_SENSOR1_CONFIG
24h SENSOR2_CONFIG Sensor 2 cycle count, frequency, RP range #LDC3114_LDC3114_LDC3114_SENSOR2_CONFIG
25h FTF0 Sensor 0 fast tracking factor for button algorithm #LDC3114_LDC3114_LDC3114_FTF0
26h SENSOR3_CONFIG Sensor3 cycle count, frequency, RP range #LDC3114_LDC3114_LDC3114_SENSOR3_CONFIG
28h FTF1_2 Sensors 1 and 2 fast tracking factors for button algorithm #LDC3114_LDC3114_LDC3114_FTF1_2
2Bh FTF3 Sensor 3 fast tracking factor for button algorithm #LDC3114_LDC3114_LDC3114_FTF3
59h RAW_DATA0_3 Sensor 0 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA0_3
5Ah RAW_DATA0_2 Sensor 0 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA0_2
5Bh RAW_DATA0_1 Sensor 0 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA0_1
5Ch RAW_DATA1_3 Sensor 1 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA1_3
5Dh RAW_DATA1_2 Sensor 1 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA1_2
5Eh RAW_DATA1_1 Sensor 1 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA1_1
5Fh RAW_DATA2_3 Sensor 2 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA2_3
60h RAW_DATA2_2 Sensor 2 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA2_2
61h RAW_DATA2_1 Sensor 2 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA2_1
62h RAW_DATA3_3 Sensor 3 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA3_3
63h RAW_DATA3_2 Sensor 3 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA3_2
64h RAW_DATA3_1 Sensor 3 pre-processed raw data #LDC3114_LDC3114_LDC3114_RAW_DATA3_1
FCh MANUFACTURER_ID_LSB Manufacturer ID lower byte #LDC3114_LDC3114_LDC3114_MANUFACTURER_ID_LSB
FDh MANUFACTURER_ID_MSB Manufacturer ID upper byte #LDC3114_LDC3114_LDC3114_MANUFACTURER_ID_MSB
FEh DEVICE_ID_LSB Device ID lower byte #LDC3114_LDC3114_LDC3114_DEVICE_ID_LSB
FFh DEVICE_ID_MSB Device ID upper byte #LDC3114_LDC3114_LDC3114_DEVICE_ID_MSB

Complex bit access types are encoded to fit into small table cells. #LDC3114_LDC3114_LEGEND shows the codes that are used for access types in this section.

Table 7-2 LDC3114 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.5.1.1 STATUS Register (Offset = 0h) [Reset = 40h]

STATUS is shown in #LDC3114_LDC3114_LDC3114_STATUS_TABLE.

Return to the Summary Table.

Device status

Table 7-3 STATUS Register Field Descriptions
Bit Field Type Reset Description
7 OUT_STATUS R 0h Output Status
Logic OR of output OUTx bits. This field is cleared by reading this register.
6 CHIP_READY R 1h Chip Ready Status

0h = Chip not ready after internal reset

1h = Chip ready after internal reset

5 RDY_TO_WRITE R 0h Ready to Write
Indicates if registers are ready to be written. See I2C Interface section for more information.

0h = Registers not ready

1h = Registers ready

4 MAXOUT R 0h Maximum Output Code
Indicates if any channel button output data reaches the maximum value (+0x7FF or -0x800). Cleared by a read of the status register.

0h = No maximum output code

1h = Maximum output code

3 FSM_WD R 0h Finite-State Machine Watchdog Error
Reports an error has occurred and conversions have been halted. Cleared by a read of the status register.

0h = No error in finite-state machine

1h = Error in finite-state machine

2 LC_WD R 0h LC Sensor Watchdog Error
Reports an error when any LC oscillator fails to start. Cleared by a read of the status register.

0h = No error in LC oscillator initialization

1h = Error in LC oscillator initialization

1 TIMEOUT R 0h Button Timeout
Reports when any button is asserted for more than 50 seconds. Cleared by a read of the status register. When DIS_BTN_TO is set, no timeout is asserted

0h = no timeout error

1h = timeout error

0 REGISTER_FLAG R 0h Register Integrity Flag
Reports if any register's value has an unexpected change. Cleared by a read of the status register.

0h = No unexpected register change

1h = Unexpected register change

7.5.1.2 OUT Register (Offset = 1h) [Reset = 00h]

OUT is shown in #LDC3114_LDC3114_LDC3114_OUT_TABLE.

Return to the Summary Table.

Channel output logic states

Table 7-4 OUT Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0h Reserved
4 DATA_RDY R 0h Output Logic State for pre-processed data capture for any enabled channel. Bit cleared on read.

0h = Data Capture in progress

1h = New Data available

3 OUT3 R 0h Button output output Logic State for Channel 3

0h = No button press detected on Channel 3

1h = Button press detected on Channel 3

2 OUT2 R 0h Button output Logic State for Channel 2

0h = No button press detected on Channel 2

1h = Button press detected on Channel 2

1 OUT1 R 0h Button output Logic State for Channel 1

0h = No button press detected on Channel 1

1h = Button press detected on Channel 1

0 OUT0 R 0h Button output Logic State for Channel 0

0h = No button press detected on Channel 0

1h = Button press detected on Channel 0.

7.5.1.3 DATA0_LSB Register (Offset = 2h) [Reset = 00h]

DATA0_LSB is shown in #LDC3114_LDC3114_LDC3114_DATA0_LSB_TABLE.

Return to the Summary Table.

The lower 8 bits of the Button 0 data (Two's complement

Table 7-5 DATA0_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DATA0[7:0] R 0h The lower 8 bits of Channel 0 button data (Two's complement).

7.5.1.4 DATA0_MSB Register (Offset = 3h) [Reset = 00h]

DATA0_MSB is shown in #LDC3114_LDC3114_LDC3114_DATA0_MSB_TABLE.

Return to the Summary Table.

The upper 4 bits of the Button 0 data (Two's complement)

Table 7-6 DATA0_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-0 DATA0[11:8] R 0h The upper 4 bits of Channel 0 button data (Two's complement).

7.5.1.5 DATA1_LSB Register (Offset = 4h) [Reset = 00h]

DATA1_LSB is shown in #LDC3114_LDC3114_LDC3114_DATA1_LSB_TABLE.

Return to the Summary Table.

The lower 8 bits of the Button 1 data (Two's complement)

Table 7-7 DATA1_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DATA1[7:0] R 0h The lower 8 bits of Channel 1 button data (Two's complement).

7.5.1.6 DATA1_MSB Register (Offset = 5h) [Reset = 00h]

DATA1_MSB is shown in #LDC3114_LDC3114_LDC3114_DATA1_MSB_TABLE.

Return to the Summary Table.

The upper 4 bits of the Button 1 data (Two's complement)

Table 7-8 DATA1_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-0 DATA1[11:8] R 0h The upper 4 bits of Channel 1 button data (Two's complement).

7.5.1.7 DATA2_LSB Register (Offset = 6h) [Reset = 00h]

DATA2_LSB is shown in #LDC3114_LDC3114_LDC3114_DATA2_LSB_TABLE.

Return to the Summary Table.

The lower 8 bits of the Button 2 data (Two's complement)

Table 7-9 DATA2_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DATA2[7:0] R 0h The lower 8 bits of Channel 2 button data (Two's complement).

7.5.1.8 DATA2_MSB Register (Offset = 7h) [Reset = 00h]

DATA2_MSB is shown in #LDC3114_LDC3114_LDC3114_DATA2_MSB_TABLE.

Return to the Summary Table.

The upper 4 bits of the Button 2 data (Two's complement)

Table 7-10 DATA2_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-0 DATA2[11:8] R 0h The upper 4 bits of Channel 2 button data (Two's complement).

7.5.1.9 DATA3_LSB Register (Offset = 8h) [Reset = 00h]

DATA3_LSB is shown in #LDC3114_LDC3114_LDC3114_DATA3_LSB_TABLE.

Return to the Summary Table.

The lower 8 bits of the Button 3 data (Two's complement)

Table 7-11 DATA3_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DATA3[7:0] R 0h The lower 8 bits of Channel 3 button data (Two's complement).

7.5.1.10 DATA3_MSB Register (Offset = 9h) [Reset = 00h]

DATA3_MSB is shown in #LDC3114_LDC3114_LDC3114_DATA3_MSB_TABLE.

Return to the Summary Table.

The upper 4 bits of the Button 3 data (Two's complement)

Table 7-12 DATA3_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-0 DATA3[11:8] R 0h The upper 4 bits of Channel 3 button data (Two's complement).

7.5.1.11 RESET Register (Offset = Ah) [Reset = 00h]

RESET is shown in #LDC3114_LDC3114_LDC3114_RESET_TABLE.

Return to the Summary Table.

Reset device and register configurations

Table 7-13 RESET Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 0h Reserved
4 FULL_RESET R/W 0h Device Reset

0h = Normal operation

1h = Resets the device and register configurations. All registers will be returned to default values. Normal operation will not resume until STATUS:CHIP_READY = 1.

3-1 RESERVED R/W 0h Reserved
0 CONFIG_MODE R/W 0h Configuration Mode
Any device configuration changes should be made with this bit set to 1. After all configuration changes have been written, set this bit to 0 for normal operation.

0h = Normal operation

1h = Holds the device in configuration mode (no data conversion), but maintains current register configurations.

7.5.1.12 EN Register (Offset = Ch) [Reset = 1Fh]

EN is shown in #LDC3114_LDC3114_LDC3114_EN_TABLE.

Return to the Summary Table.

Enable channels and low power modes

Table 7-14 EN Register Field Descriptions
Bit Field Type Reset Description
7 LPEN3 R/W 0h Channel 3 Low-Power-Enable

0h = Disable Channel 3 in Low Power Mode

1h = Enable Channel 3 in Low Power Mode. EN3 must also be set to 1.

6 LPEN2 R/W 0h Channel 2 Low-Power-Enable

0h = Disable Channel 2 in Low Power Mode

1h = Enable Channel 2 in Low Power Mode. EN2 must also be set to 1.

5 LPEN1 R/W 0h Channel 1 Low-Power-Enable

0h = Disable Channel 1 in Low Power Mode

1h = Enable Channel 1 in Low Power Mode. EN1 must also be set to 1.

4 LPEN0 R/W 1h Channel 0 Low-Power-Enable

0h = Disable Channel 0 in Low Power Mode

1h = Enable Channel 0 in Low Power Mode. EN0 must also be set to 1.

3 EN3 R/W 1h Channel 3 Enable

0h = Disable Channel 2

1h = Enable Channel 2

2 EN2 R/W 1h Channel 2 Enable

0h = Disable Channel 2

1h = Enable Channel 2

1 EN1 R/W 1h Channel 1 Enable

0h = Disable Channel 1

1h = Enable Channel 1

0 EN0 R/W 1h Channel 0 Enable

0h = Disable Channel 0

1h = Enable Channel 0

7.5.1.13 NP_SCAN_RATE Register (Offset = Dh) [Reset = 01h]

NP_SCAN_RATE is shown in #LDC3114_LDC3114_LDC3114_NP_SCAN_RATE_TABLE.

Return to the Summary Table.

Normal Power Mode scan rate

Table 7-15 NP_SCAN_RATE Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0h Reserved
3 NPFSR R/W 0h Normal Power Mode Fast Scan Rate of 160SPS. When set, this bit will override setting in NPSR only and not NPCS.
2 NPCS R/W 0h Continuous key scan in Normal Power mode When set, the scan cycle is continuous without delay in the Normal Power mode. The base increment value is fixed. This bit has no effect if the chip is in Low Power mode. This bit will override the setting in NPSR and NPFSR registers.
1-0 NPSR R/W 1h Normal Power Mode Scan Rate
Refer to Configuring Button Scan Rate section for more information.

0h = 80 SPS

1h = 40 SPS (Default)

2h = 20 SPS

3h = 10 SPS

7.5.1.14 GAIN0 Register (Offset = Eh) [Reset = 28h]

GAIN0 is shown in #LDC3114_LDC3114_LDC3114_GAIN0_TABLE.

Return to the Summary Table.

Gain for Channel 0 sensitivity adjustment for button algorithm

Table 7-16 GAIN0 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 0h Reserved
5-0 GAIN0 R/W 28h Gain for Button Data for Channel 0
Refer to the Gain Table for detailed configuration.

7.5.1.15 LP_SCAN_RATE Register (Offset = Fh) [Reset = 10h]

LP_SCAN_RATE is shown in #LDC3114_LDC3114_LDC3114_LP_SCAN_RATE_TABLE.

Return to the Summary Table.

Low Power Mode scan rate

Table 7-17 LP_SCAN_RATE Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R/W 4h Reserved
1-0 LPSR R/W 0h Low Power Mode Scan Rate
Refer to Configuring Button Scan Rate section for more information.

0h = 5 SPS

1h = 2.5 SPS

2h = 1.25 SPS (Default)

3h = 0.625 SPS

7.5.1.16 GAIN1 Register (Offset = 10h) [Reset = 28h]

GAIN1 is shown in #LDC3114_LDC3114_LDC3114_GAIN1_TABLE.

Return to the Summary Table.

Gain for Channel 1 sensitivity adjustment for button algorithm

Table 7-18 GAIN1 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 0h Reserved
5-0 GAIN1 R/W 28h Gain for Button Data for Channel 1
Refer to the Gain Table for detailed configuration.

7.5.1.17 INTPOL Register (Offset = 11h) [Reset = 18h]

INTPOL is shown in #LDC3114_LDC3114_LDC3114_INTPOL_TABLE.

Return to the Summary Table.

Interrupt polarity

Table 7-19 INTPOL Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 0h Reserved
4 BTSRT_EN R/W 1h Enable reset of button algorithm baseline tracking value
When this bit is not set, during transition between normal power mode to low power mode and back to normal power mode only baseline tracking value for enabled channels not reset. Other values in the button algorithm for calculating button press are reset even if this bit is not set.

0h = Disable Button Algorithm Restart

1h = Enable Button Algorithm Restart

3 BTN_ALG_EN R/W 1h Enable button press detection algorithm to assert events on OUT_x pins
When disabled, raw pre-processed data can be accessed via RAW_DATAx registers.
When disabled, interrupt on INTB pin is asserted when pre-processed data capture is complete after active window period completion for any of the enabled channels or for error events.
When disabled, events on OUT_x pins pins are ignored to assert interrupt on INTB pin

0h = Disable Button Algorithm

1h = Enable Button Algorithm

2 INTPOL R/W 0h Interrupt Polarity

0h = Set INTB pin polarity to active low

1h = Set INTB pin polarity to active high.

1 DIS_BTN_TO R/W 0h Disable Button time-out if if button pressed for more than 50s.

0h = Enable Button Timeout

1h = Disable Button Timeout

0 DIS_BTB_MO R/W 0h Disable setting MAXOUT bit if button algorithm generates codes outside maximum range.

0h = Enable MAXOUT check

1h = Disable MAXOUT check

7.5.1.18 GAIN2 Register (Offset = 12h) [Reset = 28h]

GAIN2 is shown in #LDC3114_LDC3114_LDC3114_GAIN2_TABLE.

Return to the Summary Table.

Gain for Channel 2 sensitivity adjustment for button algorithm

Table 7-20 GAIN2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 0h Reserved
5-0 GAIN2 R/W 28h Gain for Button Data for Channel 2
Refer to the Gain Table for detailed configuration.

7.5.1.19 LP_BASE_INC Register (Offset = 13h) [Reset = 05h]

LP_BASE_INC is shown in #LDC3114_LDC3114_LDC3114_LP_BASE_INC_TABLE.

Return to the Summary Table.

Low power base increment for button algorithm

Table 7-21 LP_BASE_INC Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R/W 0h Reserved
2-0 LPBI R/W 5h Baseline Tracking Increment for button algorithm in Low Power Mode

7.5.1.20 GAIN3 Register (Offset = 14h) [Reset = 28h]

GAIN3 is shown in #LDC3114_LDC3114_LDC3114_GAIN3_TABLE.

Return to the Summary Table.

Gain for Channel 3 sensitivity adjustment for button algorithm

Table 7-22 GAIN3 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 0h Reserved
5-0 GAIN3 R/W 28h Gain for Button Data for Channel 3
Refer to the Gain Table for detailed configuration.

7.5.1.21 NP_BASE_INC Register (Offset = 15h) [Reset = 03h]

NP_BASE_INC is shown in #LDC3114_LDC3114_LDC3114_NP_BASE_INC_TABLE.

Return to the Summary Table.

Normal power base increment for button algorithm

Table 7-23 NP_BASE_INC Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R/W 0h Reserved
2-0 NPBI R/W 3h Baseline Tracking Increment in Normal Power Mode for button algorithm
Refer to Tracking Baseline section for more information.

7.5.1.22 BTPAUSE_MAXWIN Register (Offset = 16h) [Reset = 00h]

BTPAUSE_MAXWIN is shown in #LDC3114_LDC3114_LDC3114_BTPAUSE_MAXWIN_TABLE.

Return to the Summary Table.

Baseline tracking pause and Max-win for button algorithm

Table 7-24 BTPAUSE_MAXWIN Register Field Descriptions
Bit Field Type Reset Description
7 BTPAUSE3 R/W 0h Baseline Tracking Pause for Channel 3
Pauses baseline tracking for button algorithm for Channel 3 when OUT3 is asserted. Refer to Tracking Baseline section for more information.

0h = Normal baseline tracking for Channel 1 regardless of OUT3 status.

1h = Pauses baseline tracking for Channel 1 when OUT3 is asserted.

6 BTPAUSE2 R/W 0h Baseline Tracking Pause for Channel 2
Pauses baseline tracking for button algorithm for Channel 2 when OUT2 is asserted. Refer to Tracking Baseline section for more information.

0h = Normal baseline tracking for Channel 1 regardless of OUT2 status.

1h = Pauses baseline tracking for Channel 1 when OUT2 is asserted.

5 BTPAUSE1 R/W 0h Baseline Tracking Pause for Channel 1
Pauses baseline tracking for button algorithm for Channel 1 when OUT1 is asserted. Refer to Tracking Baseline section for more information.

0h = Normal baseline tracking for Channel 1 regardless of OUT1 status.

1h = Pauses baseline tracking for Channel 1 when OUT1 is asserted.

4 BTPAUSE0 R/W 0h Baseline Tracking Pause for Channel 0
Pauses baseline tracking for button algorithm for Channel 0 when OUT0 is asserted. Refer to Tracking Baseline section for more information.

0h = Normal baseline tracking for Channel 0 regardless of OUT0 status.

1h = Pauses baseline tracking for Channel 0 when OUT0 is asserted.

3 MAXWIN3 R/W 0h Max-Win Button Algorithm Setting for Channel 3
Refer to Resolving Simultaneous Button Presses (Max-Win) section for more information.

0h = Exclude Channel 3 from the max-win group

1h = Include Channel 3 in the max-win group

2 MAXWIN2 R/W 0h Max-Win Button Algorithm Setting for Channel 2
Refer to Resolving Simultaneous Button Presses (Max-Win) section for more information.

0h = Exclude Channel 2 from the max-win group

1h = Include Channel 2 in the max-win group

1 MAXWIN1 R/W 0h Max-Win Button Algorithm Setting for Channel 1
Refer to Resolving Simultaneous Button Presses (Max-Win) section for more information.

0h = Exclude Channel 1 from the max-win group

1h = Include Channel 1 in the max-win group

0 MAXWIN0 R/W 0h Max-Win Button Algorithm Setting for Channel 0
Refer to Resolving Simultaneous Button Presses (Max-Win) section for more information.

0h = Exclude Channel 0 from the max-win group

1h = Include Channel 0 in the max-win group

7.5.1.23 LC_DIVIDER Register (Offset = 17h) [Reset = 03h]

LC_DIVIDER is shown in #LDC3114_LDC3114_LDC3114_LC_DIVIDER_TABLE.

Return to the Summary Table.

LC oscillation frequency divider

Table 7-25 LC_DIVIDER Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R/W 0h Reserved
2-0 LCDIV R/W 3h LC Oscillation Frequency Divider
The frequency divider sets the button sampling window in conjunction with SENCYCn

7.5.1.24 HYST Register (Offset = 18h) [Reset = 08h]

HYST is shown in #LDC3114_LDC3114_LDC3114_HYST_TABLE.

Return to the Summary Table.

Hysteresis for threshold for button algorithm

Table 7-26 HYST Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0h Reserved
3-0 HYST R/W 8h Hysteresis
Defines the hysteresis for button triggering threshold.
Hysteresis = HYST ´ 4
Refer to Setting Button Triggering Threshold section for more information.

7.5.1.25 TWIST Register (Offset = 19h) [Reset = 00h]

TWIST is shown in #LDC3114_LDC3114_LDC3114_TWIST_TABLE.

Return to the Summary Table.

Anti-twist for button algorithm

Table 7-27 TWIST Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R/W 0h Reserved
2-0 ANTITWIST R/W 0h Anti-Twist
When set to 0, the anti-twist for button algorithm is not enabled. When greater than 0, all buttons are enabled for the anti-twist button algorithm. The validation of all buttons is void if any button 's BTN_DATA is negative by a threshold.
Anti-twist Threshold = ANTITWIST × 4.
Refer to Overcoming Case Twisting (Anti-Twist) section for more information.

7.5.1.26 COMMON_DEFORM Register (Offset = 1Ah) [Reset = 00h]

COMMON_DEFORM is shown in #LDC3114_LDC3114_LDC3114_COMMON_DEFORM_TABLE.

Return to the Summary Table.

Anti-common and anti-deformation for button algorithm

Table 7-28 COMMON_DEFORM Register Field Descriptions
Bit Field Type Reset Description
7 ANTICOM3 R/W 0h Anti-Common Button Algorithm Setting for Channel 3
Refer to Eliminating Common-Mode Change (Anti-Common) section for more information.

0h = Exclude Channel 3 from the anti-common group.

1h = Include Channel 3 in the anti-common group.

6 ANTICOM2 R/W 0h Anti-Common Button Algorithm Setting for Channel 2
Refer to Eliminating Common-Mode Change (Anti-Common) section for more information.

0h = Exclude Channel 2 from the anti-common group.

1h = Include Channel 2 in the anti-common group.

5 ANTICOM1 R/W 0h Anti-Common Button Algorithm Setting for Channel 1
Refer to Eliminating Common-Mode Change (Anti-Common) section for more information.

0h = Exclude Channel 1 from the anti-common group.

1h = Include Channel 1 in the anti-common group.

4 ANTICOM0 R/W 0h Anti-Common Button Algorithm Setting for Channel 0
Refer to Eliminating Common-Mode Change (Anti-Common) section for more information.

0h = Exclude Channel 0 from the anti-common group.

1h = Include Channel 0 in the anti-common group.

3 ANTIDFORM3 R/W 0h Anti-Deform Button Algorithm Setting for Channel 3
Refer to Mitigating Metal Deformation (Anti-Deform) section for more information.

0h = Exclude Channel 3 from the anti-deform group.

1h = Include Channel 3 in the anti-deform group.

2 ANTIDFORM2 R/W 0h Anti-Deform Button Algorithm Setting for Channel 2
Refer to Mitigating Metal Deformation (Anti-Deform) section for more information.

0h = Exclude Channel 2 from the anti-deform group.

1h = Include Channel 2 in the anti-deform group.

1 ANTIDFORM1 R/W 0h Anti-Deform Button Algorithm Setting for Channel 1
Refer to Mitigating Metal Deformation (Anti-Deform) section for more information.

0h = Exclude Channel 1 from the anti-deform group.

1h = Include Channel 1 in the anti-deform group.

0 ANTIDFORM0 R/W 0h Anti-Deform Button Algorithm Setting for Channel 0
Refer to Mitigating Metal Deformation (Anti-Deform) section for more information.

0h = Exclude Channel 0 from the anti-deform group.

1h = Include Channel 0 in the anti-deform group.

7.5.1.27 OPOL_DPOL Register (Offset = 1Ch) [Reset = 0Fh]

OPOL_DPOL is shown in #LDC3114_LDC3114_LDC3114_OPOL_DPOL_TABLE.

Return to the Summary Table.

Output polarity for button data and output

Table 7-29 OPOL_DPOL Register Field Descriptions
Bit Field Type Reset Description
7 OPOL3 R/W 0h Button Output Polarity for OUT3 Pin

0h = Active low (Default)

1h = Active high

6 OPOL2 R/W 0h Button Output Polarity for OUT2 Pin

0h = Active low (Default)

1h = Active high

5 OPOL1 R/W 0h Button Output Polarity for OUT1 Pin

0h = Active low (Default)

1h = Active high

4 OPOL0 R/W 0h Button Output Polarity for OUT0 Pin

0h = Active low (Default)

1h = Active high

3 DPOL3 R/W 1h Processed Button Algorithm Data Polarity for Channel 3

0h = BTN_DATA3 decreases as fSENSOR3 increases

1h = DATA3 increases as fSENSOR3 increases.

2 DPOL2 R/W 1h Processed Button Algorithm Data Polarity for Channel 2

0h = BTN_DATA2 decreases as fSENSOR2 increases

1h = DATA2 increases as fSENSOR2 increases.

1 DPOL1 R/W 1h Processed Button Algorithm Data Polarity for Channel 1

0h = BTN_DATA1 decreases as fSENSOR1 increases

1h = DATA1 increases as fSENSOR1 increases.

0 DPOL0 R/W 1h Processed Button Algorithm Data Polarity for Channel 0

0h = BTN_DATA0 decreases as fSENSOR0 increases

1h = DATA0 increases as fSENSOR0 increases.

7.5.1.28 CNTSC Register (Offset = 1Eh) [Reset = 55h]

CNTSC is shown in #LDC3114_LDC3114_LDC3114_CNTSC_TABLE.

Return to the Summary Table.

Counter scale

Table 7-30 CNTSC Register Field Descriptions
Bit Field Type Reset Description
7-6 CNTSC3 R/W 1h Counter Scale for Channel 3
Refer to Scaling Frequency Counter Output section for more information.

0h = CNTSC3 is 0

1h = CNTSC3 is 1

2h = CNTSC3 is 2

3h = CNTSC3 is 3

5-4 CNTSC2 R/W 1h Counter Scale for Channel 2
Refer to Scaling Frequency Counter Output section for more information.

0h = CNTSC2 is 0

1h = CNTSC2 is 1

2h = CNTSC2 is 2

3h = CNTSC2 is 3

3-2 CNTSC1 R/W 1h Counter Scale for Channel 1
Refer to Scaling Frequency Counter Output section for more information.

0h = CNTSC1 is 0

1h = CNTSC1 is 1

2h = CNTSC1 is 2

3h = CNTSC1 is 3

1-0 CNTSC0 R/W 1h Counter Scale for Channel 0
Refer to Scaling Frequency Counter Output section for more information.

0h = CNTSC0 is 0

1h = CNTSC0 is 1

2h = CNTSC0 is 2

3h = CNTSC0 is 3

7.5.1.29 SENSOR0_CONFIG Register (Offset = 20h) [Reset = 04h]

SENSOR0_CONFIG is shown in #LDC3114_LDC3114_LDC3114_SENSOR0_CONFIG_TABLE.

Return to the Summary Table.

Sensor 0 cycle count, frequency, RP range

Table 7-31 SENSOR0_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7 RP0 R/W 0h Channel 0 Sensor Rp Range Select
Set based on the actual sensor Rp physical parameter.
Refer to Designing Sensor Parameters section for more information.

0h = 50 Ω ≤ Rp ≤ 4 kΩ (Default)

1h = 800 Ω ≤ Rp ≤ 10 kΩ

6-5 FREQ0 R/W 0h Channel 0 Sensor Frequency Range Select
Refer to Designing Sensor Parameterssection for more information.

0h = 1 MHz to 3.3 MHz

1h = 3.3 MHz to 10 MHz

2h = 10 MHz to 30 MHz

3h = Reserved

4-0 SENCYC0 R/W 4h Channel 0 Sensor Cycle Count
SENCYC0 sets the Channel 0 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window section for more information.

7.5.1.30 SENSOR1_CONFIG Register (Offset = 22h) [Reset = 04h]

SENSOR1_CONFIG is shown in #LDC3114_LDC3114_LDC3114_SENSOR1_CONFIG_TABLE.

Return to the Summary Table.

Sensor 1 cycle count, frequency, RP range

Table 7-32 SENSOR1_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7 RP1 R/W 0h Channel 1 Sensor Rp Range Select
Set based on the actual sensor Rp physical parameter.
Refer to Designing Sensor Parameters section for more information.

0h = 50 Ω ≤ Rp ≤ 4 kΩ (Default)

1h = 800 Ω ≤ Rp ≤ 10 kΩ

6-5 FREQ1 R/W 0h Channel 1 Sensor Frequency Range Select
Refer to Designing Sensor Parameterssection for more information.

0h = 1 MHz to 3.3 MHz

1h = 3.3 MHz to 10 MHz

2h = 10 MHz to 30 MHz

3h = Reserved

4-0 SENCYC1 R/W 4h Channel 1 Sensor Cycle Count
SENCYC1 sets the Channel 1 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window section for more information.

7.5.1.31 SENSOR2_CONFIG Register (Offset = 24h) [Reset = 04h]

SENSOR2_CONFIG is shown in #LDC3114_LDC3114_LDC3114_SENSOR2_CONFIG_TABLE.

Return to the Summary Table.

Sensor 2 cycle count, frequency, RP range

Table 7-33 SENSOR2_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7 RP2 R/W 0h Channel 2 Sensor Rp Range Select
Set based on the actual sensor Rp physical parameter.
Refer to Designing Sensor Parameters section for more information.

0h = 50 Ω ≤ Rp ≤ 4 kΩ (Default)

1h = 800 Ω ≤ Rp ≤ 10 kΩ

6-5 FREQ2 R/W 0h Channel 2 Sensor Frequency Range Select
Refer to Designing Sensor Parameterssection for more information.

0h = 1 MHz to 3.3 MHz

1h = 3.3 MHz to 10 MHz

2h = 10 MHz to 30 MHz

3h = Reserved

4-0 SENCYC2 R/W 4h Channel 2 Sensor Cycle Count
SENCYC2 sets the Channel 2 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window section for more information.

7.5.1.32 FTF0 Register (Offset = 25h) [Reset = DAh]

FTF0 is shown in #LDC3114_LDC3114_LDC3114_FTF0_TABLE.

Return to the Summary Table.

Sensor 0 fast tracking factor for button algorithm

Table 7-34 FTF0 Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R/W 1Bh Reserved
2-1 FTF0 R/W 1h Fast Tracking Factor for Channel 0
Defines baseline tracking for button algorithm speed for negative values of DATA0.
Refer to Tracking Baseline section for more information.

0h = FTF0 is 0

1h = FTF0 is 1

2h = FTF0 is 2

3h = FTF0 is 3

0 RESERVED R/W 0h Reserved

7.5.1.33 SENSOR3_CONFIG Register (Offset = 26h) [Reset = 04h]

SENSOR3_CONFIG is shown in #LDC3114_LDC3114_LDC3114_SENSOR3_CONFIG_TABLE.

Return to the Summary Table.

Sensor3 cycle count, frequency, RP range

Table 7-35 SENSOR3_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7 RP3 R/W 0h Channel 3 Sensor Rp Range Select
Set based on the actual sensor Rp physical parameter.
Refer to Designing Sensor Parameters section for more information.

0h = 50 Ω ≤ Rp ≤ 4 kΩ (Default)

1h = 800 Ω ≤ Rp ≤ 10 kΩ

6-5 FREQ3 R/W 0h Channel 3 Sensor Frequency Range Select
Refer to Designing Sensor Parameters section for more information.

0h = 1 MHz to 3.3 MHz

1h = 3.3 MHz to 10 MHz

2h = 10 MHz to 30 MHz

3h = Reserved

4-0 SENCYC3 R/W 4h Channel 3 Sensor Cycle Count
SENCYC3 sets the Channel 3 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window section for more information.

7.5.1.34 FTF1_2 Register (Offset = 28h) [Reset = 50h]

FTF1_2 is shown in #LDC3114_LDC3114_LDC3114_FTF1_2_TABLE.

Return to the Summary Table.

Sensors 1 and 2 fast tracking factors for button algorithm

Table 7-36 FTF1_2 Register Field Descriptions
Bit Field Type Reset Description
7-6 FTF2 R/W 1h Fast Tracking Factor for Channel 2
Defines baseline tracking for button algorithm speed for negative values of DATA2.
Refer to Tracking Baseline section for more information.

0h = FTF2 is 0

1h = FTF2 is 1

2h = FTF2 is 2

3h = FTF2 is 3

5-4 FTF1 R/W 1h Fast Tracking Factor for Channel 0
Defines baseline tracking for button algorithm speed for negative values of DATA1.
Refer to Tracking Baseline section for more information.

0h = FTF1 is 0

1h = FTF1 is 1

2h = FTF1 is 2

3h = FTF1 is 3

3-0 RESERVED R/W 0h Reserved

7.5.1.35 FTF3 Register (Offset = 2Bh) [Reset = 01h]

FTF3 is shown in #LDC3114_LDC3114_LDC3114_FTF3_TABLE.

Return to the Summary Table.

Sensor 3 fast tracking factor for button algorithm

Table 7-37 FTF3 Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R/W 0h Reserved
1-0 FTF3 R/W 1h Fast Tracking Factor for Channel 3
Defines baseline tracking for button algorithm speed for negative values of DATA3.
Refer to Tracking Baseline section for more information.

0h = FTF3 is 0

1h = FTF3 is 1

2h = FTF3 is 2

3h = FTF3 is 3

7.5.1.36 RAW_DATA0_3 Register (Offset = 59h) [Reset = 00h]

RAW_DATA0_3 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA0_3_TABLE.

Return to the Summary Table.

Sensor 0 pre-processed raw data

Table 7-38 RAW_DATA0_3 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA0[7:0] R 0h Sensor 0 pre-processed raw data

7.5.1.37 RAW_DATA0_2 Register (Offset = 5Ah) [Reset = 00h]

RAW_DATA0_2 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA0_2_TABLE.

Return to the Summary Table.

Sensor 0 pre-processed raw data

Table 7-39 RAW_DATA0_2 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA0[15:8] R 0h Sensor 0 pre-processed raw data

7.5.1.38 RAW_DATA0_1 Register (Offset = 5Bh) [Reset = 00h]

RAW_DATA0_1 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA0_1_TABLE.

Return to the Summary Table.

Sensor 0 pre-processed raw data

Table 7-40 RAW_DATA0_1 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA0[23:16] R 0h Sensor 0 pre-processed raw data

7.5.1.39 RAW_DATA1_3 Register (Offset = 5Ch) [Reset = 00h]

RAW_DATA1_3 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA1_3_TABLE.

Return to the Summary Table.

Sensor 1 pre-processed raw data

Table 7-41 RAW_DATA1_3 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA1[7:0] R 0h Sensor 1 pre-processed raw data

7.5.1.40 RAW_DATA1_2 Register (Offset = 5Dh) [Reset = 00h]

RAW_DATA1_2 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA1_2_TABLE.

Return to the Summary Table.

Sensor 1 pre-processed raw data

Table 7-42 RAW_DATA1_2 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA1[15:8] R 0h Sensor 1 pre-processed raw data

7.5.1.41 RAW_DATA1_1 Register (Offset = 5Eh) [Reset = 00h]

RAW_DATA1_1 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA1_1_TABLE.

Return to the Summary Table.

Sensor 1 pre-processed raw data

Table 7-43 RAW_DATA1_1 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA1[23:16] R 0h Sensor 1 pre-processed raw data

7.5.1.42 RAW_DATA2_3 Register (Offset = 5Fh) [Reset = 00h]

RAW_DATA2_3 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA2_3_TABLE.

Return to the Summary Table.

Sensor 2 pre-processed raw data

Table 7-44 RAW_DATA2_3 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA2[7:0] R 0h Sensor 2 pre-processed raw data

7.5.1.43 RAW_DATA2_2 Register (Offset = 60h) [Reset = 00h]

RAW_DATA2_2 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA2_2_TABLE.

Return to the Summary Table.

Sensor 2 pre-processed raw data

Table 7-45 RAW_DATA2_2 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA2[15:8] R 0h Sensor 2 pre-processed raw data

7.5.1.44 RAW_DATA2_1 Register (Offset = 61h) [Reset = 00h]

RAW_DATA2_1 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA2_1_TABLE.

Return to the Summary Table.

Sensor 2 pre-processed raw data

Table 7-46 RAW_DATA2_1 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA2[23:16] R 0h Sensor 2 pre-processed raw data

7.5.1.45 RAW_DATA3_3 Register (Offset = 62h) [Reset = 00h]

RAW_DATA3_3 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA3_3_TABLE.

Return to the Summary Table.

Sensor 3 pre-processed raw data

Table 7-47 RAW_DATA3_3 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA3[7:0] R 0h Sensor 3 pre-processed raw data

7.5.1.46 RAW_DATA3_2 Register (Offset = 63h) [Reset = 00h]

RAW_DATA3_2 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA3_2_TABLE.

Return to the Summary Table.

Sensor 3 pre-processed raw data

Table 7-48 RAW_DATA3_2 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA3[15:8] R 0h Sensor 3 pre-processed raw data

7.5.1.47 RAW_DATA3_1 Register (Offset = 64h) [Reset = 00h]

RAW_DATA3_1 is shown in #LDC3114_LDC3114_LDC3114_RAW_DATA3_1_TABLE.

Return to the Summary Table.

Sensor 3 pre-processed raw data

Table 7-49 RAW_DATA3_1 Register Field Descriptions
Bit Field Type Reset Description
7-0 RAW_DATA3[23:16] R 0h Sensor 3 pre-processed raw data

7.5.1.48 MANUFACTURER_ID_LSB Register (Offset = FCh) [Reset = 49h]

MANUFACTURER_ID_LSB is shown in #LDC3114_LDC3114_LDC3114_MANUFACTURER_ID_LSB_TABLE.

Return to the Summary Table.

Manufacturer ID lower byte

Table 7-50 MANUFACTURER_ID_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 MANUFACTURER_ID_[7:0] R 49h Manufacturer ID [7:0]

7.5.1.49 MANUFACTURER_ID_MSB Register (Offset = FDh) [Reset = 54h]

MANUFACTURER_ID_MSB is shown in #LDC3114_LDC3114_LDC3114_MANUFACTURER_ID_MSB_TABLE.

Return to the Summary Table.

Manufacturer ID upper byte

Table 7-51 MANUFACTURER_ID_MSB Register Field Descriptions
Bit Field Type Reset Description
7-0 MANUFACTURER_ID_[15:8] R 54h Manufacturer ID [15:8]

7.5.1.50 DEVICE_ID_LSB Register (Offset = FEh) [Reset = 00h]

DEVICE_ID_LSB is shown in #LDC3114_LDC3114_LDC3114_DEVICE_ID_LSB_TABLE.

Return to the Summary Table.

Device ID lower byte

Table 7-52 DEVICE_ID_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DEVICE_ID_[7:0] R 0h Device ID [7:0]

7.5.1.51 DEVICE_ID_MSB Register (Offset = FFh) [Reset = 40h]

DEVICE_ID_MSB is shown in #LDC3114_LDC3114_LDC3114_DEVICE_ID_MSB_TABLE.

Return to the Summary Table.

Device ID upper byte

Table 7-53 DEVICE_ID_MSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DEVICE_ID_[15:8] R 40h Device ID [15:8]