SNVS974B April   2013  – October 2015 LM3630A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C-Compatible Timing Requirements (SCL, SDA)
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
        1.  Control Bank Mapping
        2.  PWM Input Polaritiy
        3.  HWEN Input
        4.  SEL Input
        5.  INTN Output
        6.  Boost Converter
        7.  Boost Switching Frequency Select
        8.  Adaptive Headroom
        9.  Current Sinks
        10. Current String Biasing
        11. Full-Scale LED Current
        12. Brightness Register
        13. Exponential Mapping
        14. Linear Mapping
      2. 7.3.2 Test Features
        1. Open LED String (LED1 And LED2)
        2. Shorted LED String
        3. Overvoltage Protection (Manufacturing Fault Detection and Shutdown)
      3. 7.3.3 Fault Flags/Protection Features
        1. Overvoltage Protection (Inductive Boost Operation)
        2. Current Limit
        3. Thermal Shutdown
      4. 7.3.4 Initialization Timing
        1. Initialization Timing With HWEN Tied to VIN
        2. Initialization Timing With HWEN Driven by GPIO
        3. Initialization After Software Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 LED Current Ramping
        1. Start-Up/Shutdown Ramp
        2. Run-Time Ramp
      2. 7.4.2 PWM Operation
        1. PWM Input
        2. PWM Input Frequency
        3. Recommended Settings
        4. Adjustments to PWM Sampler
          1. Filter Strength, Register 50h Bits [1:0]
          2. Hysteresis 1 Bit, Register 05h, Bit 7
          3. Lower Bound Disable, Register 05h, Bit 6
        5. Minimum TON Pulse Width
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. Data Validity
        2. Start and Stop Conditions
        3. Transferring Data
    6. 7.6 Register Maps
      1. 7.6.1 LM3630A I2C Register Map
      2. 7.6.2 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Inductor Selection
        2. Maximum Power Output
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 Recommended Initialization Sequence
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Output Capacitor Placement
      2. 10.1.2 Schottky Diode Placement
      3. 10.1.3 Inductor Placement
      4. 10.1.4 Input Capacitor Selection and Placement
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The LM3630A contains an inductive boost converter which detects a high switched voltage (up to 40 V) at the SW pin, and a step current (up to 900 mA) through the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference into nearby nodes due to electric field coupling (I = CdV/dt). The large step current through the diode and the output capacitor can cause a large voltage spike at the SW pin and the OVP pin due to parasitic inductance in the step current conducting path (V = Ldi/dt). Board layout guidelines are geared towards minimizing this electric field coupling and conducted noise. Figure 92 highlights these two noise generating components.

LM3630A inductive_boost_snvs974.gif Figure 92. LM3630A Boost Converter Showing Pulsed Voltage At SW (High Dv/Dt) and
Current Through Schottky and COUT (High Di/Dt)

The following lists the main (layout sensitive) areas of the LM3630A in order of decreasing importance:

  • Output Capacitor
    • Schottky Cathode to COUT+
    • COUT– to GND
  • Schottky Diode
    • SW Pin to Schottky Anode
    • Schottky Cathode to COUT+
  • Inductor
    • SW Node PCB capacitance to other traces
  • Input Capacitor
    • CIN+ to IN pin
    • CIN– to GND

10.1.1 Output Capacitor Placement

The output capacitor is in the path of the inductor current discharge path. As a result COUT detects a high current step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series path from the cathode of the diode through COUT and back into the LM3630A GND pin will contribute to voltage spikes (VSPIKE = LP_ × dI/dt) at SW and OUT which can potentially overvoltage the SW pin, or feed through to GND. To avoid this, COUT+ must be connected as close as possible to the Cathode of the Schottky diode and COUT– must be connected as close as possible to the device GND bump. The best placement for COUT is on the same layer as the LM3630A so as to avoid any vias that can add excessive series inductance (see Figure 94).

10.1.2 Schottky Diode Placement

The Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode detects a high current step from 0 to IPEAK each time the switch turns off and the diode turns on. Any inductance in series with the diode will cause a voltage spike (VSPIKE = LP_ × dI/dt) at SW and OUT which can potentially overvoltage the SW pin, or feed through to VOUT and through the output capacitor and into GND. Connecting the anode of the diode as close as possible to the SW pin and the cathode of the diode as close as possible to COUT+ will reduce the inductance (LP_) and minimize these voltage spikes (see Figure 94).

10.1.3 Inductor Placement

The node where the inductor connects to the LM3630A SW bump has 2 issues. First, a large switched voltage (0 to VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this path can cause large voltage drops that will negatively affect efficiency.

To reduce the capacitively coupled signal from SW into nearby traces, the SW bump to inductor connection must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, the other traces need to be routed away from SW and not directly beneath. This is especially true for high impedance nodes that are more susceptible to capacitive coupling such as (SCL, SDA, HWEN, PWM, and possibly ASL1 and ALS2). A GND plane placed directly below SW will dramatically reduce the capacitive coupling from SW into nearby traces

To limit the trace resistance of the VBATT to inductor connection and from the inductor to SW connection, use short, wide traces (see Figure 94).

10.1.4 Input Capacitor Selection and Placement

The input bypass capacitor filters the inductor current ripple, and the internal MOSFET driver currents during turnon of the power switch.

The driver current requirement can range from 50 mA at 2.7 V to over 200 mA at 5.5 V with fast durations of approximately 10 ns to 20 ns. This will appear as high di/dt current pulses coming from the input capacitor each time the switch turns on. Close placement of the input capacitor to the IN pin and to the GND pin is critical since any series inductance between IN and CIN+ or CIN– and GND can create voltage spikes that could appear on the VIN supply line and in the GND plane.

Close placement of the input bypass capacitor at the input side of the inductor is also critical. The source impedance (inductance and resistance) from the input supply, along with the input capacitor of the LM3630A, form a series RLC circuit. If the output resistance from the source (RS) is low enough the circuit will be underdamped and will have a resonant frequency (typically the case). Depending on the size of LS the resonant frequency could occur below, close to, or above switching frequency of the device. This can cause the supply current ripple to be:

  1. Approximately equal to the inductor current ripple when the resonant frequency occurs well above the LM3630A switching frequency;
  2. Greater then the inductor current ripple when the resonant frequency occurs near the switching frequency; and
  3. Less then the inductor current ripple when the resonant frequency occurs well below the switching frequency.

Figure 93 shows the series RLC circuit formed from the output impedance of the supply and the input capacitor. The circuit is re-drawn for the AC case where the VIN supply is replaced with a short to GND and the LM3630A plus inductor is replaced with a current source (ΔIL). In Figure 93, equation 1 is the criteria for an underdamped response, equation 2 is the resonant frequency, and equation 3 is the approximated supply current ripple as a function of LS, RS, and CIN.

As an example, consider a 3.6-V supply with 0.1-Ω of series resistance connected to CIN through 50 nH of connecting traces. This results in an underdamped input filter circuit with a resonant frequency of 712 kHz. Since the switching frequency lies near to the resonant frequency of the input RLC network, the supply current is probably larger then the inductor current ripple. In this case using equation 2 from Figure 93 the supply current ripple can be approximated as 1.68 multiplied by the inductor current ripple. Increasing the series inductance (LS) to 500 nH causes the resonant frequency to move to around 225 kHz and the supple current ripple to be approximately 0.25 multiplied by the inductor current ripple.

LM3630A 30086628a.gif Figure 93. Input RLC Network

10.2 Layout Example

LM3630A 30200202.gif Figure 94. Typical LP3630A PCB Layout (2 × 10 Led Application)