SNVS496F January   2007  – May 2021 LM5002

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Voltage VCC Regulator
      2. 7.3.2 Oscillator
      3. 7.3.3 External Synchronization
      4. 7.3.4 Enable and Standby
      5. 7.3.5 Error Amplifier and PWM Comparator
      6. 7.3.6 Current Amplifier and Slope Compensation
      7. 7.3.7 Power MOSFET
    4. 7.4 Device Functional Modes
      1. 7.4.1 Thermal Protection
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 VIN
      2. 8.1.2 SW PIN
      3. 8.1.3 EN or UVLO Voltage Divider Selection
      4. 8.1.4 Soft Start
    2. 8.2 Typical Applications
      1. 8.2.1 Non-Isolated Flyback Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Switching Frequency
          2. 8.2.1.2.2 Flyback Transformer
          3. 8.2.1.2.3 Peak MOSFET Current
          4. 8.2.1.2.4 Output Capacitance
          5. 8.2.1.2.5 Output Diode Rating
          6. 8.2.1.2.6 Power Stage Analysis
          7. 8.2.1.2.7 Loop Compensation
      2. 8.2.2 Isolated Flyback Regulator
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 Boost Regulator
        1. 8.2.3.1 Design Requirements
      4. 8.2.4 24-V SEPIC Regulator
        1. 8.2.4.1 Design Requirements
      5. 8.2.5 12-V Automotive SEPIC Regulator
        1. 8.2.5.1 Design Requirements
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Current Amplifier and Slope Compensation

The LM5002 employs peak current-mode control that also provides a cycle-by-cycle overcurrent protection feature. An internal 100-mΩ current sense resistor measures the current in the power MOSFET source. The sense resistor voltage is amplified 30 times to provide a 3 V/A signal into the current limit comparator. Current limiting is initiated if the internal current limit comparator input exceeds the 1.5-V threshold, corresponding to
0.5 A. When the current limit comparator is triggered, the SW output pin immediately switches to a high impedance state.

The current sense signal is reduced to a scale factor of 2.1 V/A for the PWM comparator signal. The signal is then summed with a 450-mV peak slope compensation ramp. The combined signal provides the PWM comparator with a control signal that reaches 1.5 V when the MOSFET current is 0.5 A. For duty cycles greater than 50%, current mode control circuits are subject to subharmonic oscillation (alternating between short and long PWM pulses every other cycle). Adding a fixed slope voltage ramp signal (slope compensation) to the current sense signal prevents this oscillation. The 450-mV ramp (zero volts when the power MOSFET turns on, and 450 mV at the end of the PWM clock cycle) adds a fixed slope to the current sense ramp to prevent oscillation.

To prevent erratic operation at low duty cycle, a leading edge blanking circuit attenuates the current sense signal when the power MOSFET is turned on. When the MOSFET is initially turned on, current spikes from the power MOSFET drain-source and gate-source capacitances flow through the current sense resistor. These transient currents normally cease within 50 ns with proper selection of rectifier diodes and proper PCB layout.