SNVS532D October   2007  – August 2020 LM5067

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Up Sequence
      2. 8.3.2 Gate Control
      3. 8.3.3 Current Limit
      4. 8.3.4 Circuit Breaker
      5. 8.3.5 Power Limit
      6. 8.3.6 Fault Timer and Restart
      7. 8.3.7 Undervoltage Lock-Out (UVLO)
      8. 8.3.8 Overvoltage Lock-Out (OVLO)
      9. 8.3.9 Power Good Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown / Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  RIN, CIN
        2. 9.2.2.2  Current Limit, RS
        3. 9.2.2.3  Power Limit Threshold
        4. 9.2.2.4  Turn-On Time
          1. 9.2.2.4.1 Turn-on With Current Limit Only
          2. 9.2.2.4.2 Turn-on With Power Limit and Current Limit
        5. 9.2.2.5  MOSFET Selection
        6. 9.2.2.6  Timer Capacitor, CT
          1. 9.2.2.6.1 Insertion Delay
          2. 9.2.2.6.2 Fault Timeout Period
          3. 9.2.2.6.3 Restart Timing
        7. 9.2.2.7  UVLO, OVLO
          1. 9.2.2.7.1 Option A:
          2. 9.2.2.7.2 Option B:
          3. 9.2.2.7.3 Option C:
          4. 9.2.2.7.4 Option D:
        8. 9.2.2.8  Thermal Considerations
        9. 9.2.2.9  System Considerations
          1. 9.2.2.9.1 System Considerations During Surge Events
        10. 9.2.2.10 Power Good Pin
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Operating Voltage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 Fault Timer and Restart

When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is active, an 85 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 8-5 (Fault Timeout Period). If the fault condition subsides before the TIMER pin reaches 4.0V, the LM5067 returns to the normal operating mode and CT is discharged by the 2.5 µA current sink. If the TIMER pin reaches 4.0V during the Fault Timeout Period, Q1 is switched off by a 2.2 mA pull-down current at the GATE pin. The subsequent restart procedure depends on which version of the LM5067 is in use.

The LM5067-1 latches the GATE pin low at the end of the Fault Timeout Period, and CT is discharged by the 2.5 µA fault current sink. The GATE pin is held low until a power up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO/EN pin within 2.5V of VEE with an open-collector or open-drain device as shown in Figure 8-4. The voltage across CT must be <0.3V for the restart procedure to be effective.

GUID-200310B5-0928-4F2C-8A71-0D8D8AB1781E-low.gifFigure 8-4 Latched Fault Restart Control

The LM5067-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 4 V and 1.25 V seven times after the Fault Timeout Period, as shown in Figure 8-5. The period of each cycle is determined by the 85 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor CT. When the TIMER pin reaches 0.3 V during the eighth high-to-low ramp, the 52 µA current source at the GATE pin turns on Q1. If the fault condition is still present, the Fault Timeout Period and the restart cycle repeat.

GUID-EDC96FE2-C49D-4727-A9B5-883200486F17-low.gifFigure 8-5 Restart Sequence (LM5067-2)