SLVSGN5 October   2022 LM51231-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Enable/Disable (EN, VH Pin)
      2. 7.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 7.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 7.3.4  VOUT Range Selection (RANGE Pin)
      5. 7.3.5  Line Undervoltage Lockout (UVLO Pin)
      6. 7.3.6  Fast Restart using VCC HOLD (VH Pin)
      7. 7.3.7  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      8. 7.3.8  Overvoltage Protection (VOUT Pin)
      9. 7.3.9  Power Good Indicator (PGOOD Pin)
      10. 7.3.10 Dynamically Programmable Switching Frequency (RT)
      11. 7.3.11 External Clock Synchronization (SYNC Pin)
      12. 7.3.12 Programmable Spread Spectrum (DITHER Pin)
      13. 7.3.13 Programmable Soft-start (SS Pin)
      14. 7.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      15. 7.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
      16. 7.3.16 Constant Peak Current Limit (CSP, CSN Pin)
      17. 7.3.17 Maximum Duty Cycle and Minimum Controllable On-time Limits
      18. 7.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 7.3.19 Thermal Shutdown Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Status
        1. 7.4.1.1 Shutdown Mode
        2. 7.4.1.2 Configuration Mode
        3. 7.4.1.3 Active Mode
        4. 7.4.1.4 Bypass Mode
          1. 7.4.1.4.1 Bypass DE mode
          2. 7.4.1.4.2 Bypass FPWM
      2. 7.4.2 Light Load Switching Mode
        1. 7.4.2.1 Forced PWM (FPWM) Mode
        2. 7.4.2.2 Diode Emulation (DE) Mode
        3. 7.4.2.3 Forced Diode Emulation Operation in FPWM Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Ideas
      4. 8.2.4 Application Curves
    3. 8.3 System Example
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimize generation of unwanted EMI.

  • Place CVCC, CBIAS, CHB, and CVOUT as close to the device. Make direct connections to the pins.
  • Place QH, QL, and COUT. Make the switching loop (COUT to QH to QL to COUT) as small as possible. A small size ceramic capacitor helps to minimize the loop length. Leave a copper area near the drain connection of QH for a thermal dissipation.
  • Place LM, RS, and CIN. Make the loop (CIN to RS to LM to CIN) as small as possible. A small size ceramic capacitor helps to minimize the loop length.
  • Connect RS to CSP-CSN. The CSP-CSN traces must be routed in parallel and surrounded by ground.
  • Connect VOUT, HO, and SW. These traces must be routed in parallel using a short, low inductance path. VOUT must be directly connected the drain connection of QH. SW must be directly connected to the source connection of QH
  • Connect LO and PGND. The LO-PGND traces must be routed in parallel using a short, low inductance path. PGND must be directly connected the source connection of QL
  • Place RCOMP, CCOMP, CSS, CVREF, RVREFT, RVREFB, RT, and RUVLOB as close to the device, and connect to a common analog ground plane.
  • Connect power ground plane (the source connection of the QL) to EP through PGND. Connect the common analog ground plane to EP through AGND. PGND and AGND must be connected underneath the device.
  • Add several vias under EP to help conduct heat away from the device. Connect the vias to a large analog ground plane on the bottom layer.
  • Do not connect COUT and CIN grounds underneath the device and through the large analog ground plane which is connected to EP.