SLVSGN5A October   2022  – November 2025 LM51231-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Enable/Disable (EN, VH Pin)
      2. 6.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 6.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 6.3.4  VOUT Range Selection (RANGE Pin)
      5. 6.3.5  Line Undervoltage Lockout (UVLO Pin)
      6. 6.3.6  Fast Restart using VCC HOLD (VH Pin)
      7. 6.3.7  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      8. 6.3.8  Overvoltage Protection (VOUT Pin)
      9. 6.3.9  Power Good Indicator (PGOOD Pin)
      10. 6.3.10 Dynamically Programmable Switching Frequency (RT)
      11. 6.3.11 External Clock Synchronization (SYNC Pin)
      12. 6.3.12 Programmable Spread Spectrum (DITHER Pin)
      13. 6.3.13 Programmable Soft-start (SS Pin)
      14. 6.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      15. 6.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
      16. 6.3.16 Constant Peak Current Limit (CSP, CSN Pin)
      17. 6.3.17 Maximum Duty Cycle and Minimum Controllable On-time Limits
      18. 6.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 6.3.19 Thermal Shutdown Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Status
        1. 6.4.1.1 Shutdown Mode
        2. 6.4.1.2 Configuration Mode
        3. 6.4.1.3 Active Mode
        4. 6.4.1.4 Bypass Mode
          1. 6.4.1.4.1 Bypass DE mode
          2. 6.4.1.4.2 Bypass FPWM
      2. 6.4.2 Light Load Switching Mode
        1. 6.4.2.1 Forced PWM (FPWM) Mode
        2. 6.4.2.2 Diode Emulation (DE) Mode
        3. 6.4.2.3 Forced Diode Emulation Operation in FPWM Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Ideas
      4. 7.2.4 Application Curves
    3. 7.3 System Example
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.4 VOUT Range Selection (RANGE Pin)

The programmable VOUT range is selected during the device configuration and it cannot be changed until you reconfigure the device. Lower VOUT range (5V to 20V) is selected if the resistance from VREF to AGND (RVREFT + RVREFB) is in the range of 75kΩ to 100kΩ during the device configuration. Upper VOUT range (15V to 57V) is selected if the resistance from VREF to AGND is in the range of 20kΩ to 35kΩ during the device configuration. The accuracy of the VOUT regulation is within the selected range.