SLVSGN5 October   2022 LM51231-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Enable/Disable (EN, VH Pin)
      2. 7.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 7.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 7.3.4  VOUT Range Selection (RANGE Pin)
      5. 7.3.5  Line Undervoltage Lockout (UVLO Pin)
      6. 7.3.6  Fast Restart using VCC HOLD (VH Pin)
      7. 7.3.7  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      8. 7.3.8  Overvoltage Protection (VOUT Pin)
      9. 7.3.9  Power Good Indicator (PGOOD Pin)
      10. 7.3.10 Dynamically Programmable Switching Frequency (RT)
      11. 7.3.11 External Clock Synchronization (SYNC Pin)
      12. 7.3.12 Programmable Spread Spectrum (DITHER Pin)
      13. 7.3.13 Programmable Soft-start (SS Pin)
      14. 7.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      15. 7.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
      16. 7.3.16 Constant Peak Current Limit (CSP, CSN Pin)
      17. 7.3.17 Maximum Duty Cycle and Minimum Controllable On-time Limits
      18. 7.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 7.3.19 Thermal Shutdown Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Status
        1. 7.4.1.1 Shutdown Mode
        2. 7.4.1.2 Configuration Mode
        3. 7.4.1.3 Active Mode
        4. 7.4.1.4 Bypass Mode
          1. 7.4.1.4.1 Bypass DE mode
          2. 7.4.1.4.2 Bypass FPWM
      2. 7.4.2 Light Load Switching Mode
        1. 7.4.2.1 Forced PWM (FPWM) Mode
        2. 7.4.2.2 Diode Emulation (DE) Mode
        3. 7.4.2.3 Forced Diode Emulation Operation in FPWM Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Ideas
      4. 8.2.4 Application Curves
    3. 8.3 System Example
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)

The VOUT regulation target (VOUT-REG) is adjustable by programming the TRK pin voltage which is the reference of the internal error amplifier. The accuracy of VOUT-REG is ensured when the TRK voltage is between 0.25 V and 1.0 V. If the VOUT regulation set point is set outside of the VOUT range selection, VOUT is still regulated. The high impedance TRK pin allows users to program the pin voltage directly by a D/A converter or by connecting to a resistor voltage divider (RVREFT, RVREFB) between VREF and AGND. See Figure 7-6.

The device provides a 1-V voltage reference (VREF) which can be used to program the TRK pin voltage through a resistor voltage divider. It is not recommended to use VREF as a reference voltage of an external circuit. For stability reasons the VREF capacitor (CVREF) should be between 330 pF and 1 nF, 470 pF are recommended.

When RVREFT and RVREFB are used to program the TRK pin voltage, VOUT-REG can be calculated as follows.

Lower VOUT Range
Equation 4. V O U T _ R E G = 20 × R V R E F B R V R E F B + R V R E F T
Upper VOUT Range
Equation 5. V O U T _ R E G = 60 × R V R E F B R V R E F B + R V R E F T

The TRK pin voltage can be dynamically programmed in active mode, which makes an envelope tracking power supply design easy. When designing a tracking power supply, it is required to adjust the TRK pin voltage slow enough so that the VOUT pin voltage can track the command and the internal overvoltage or undervoltage comparator is not triggered during the transient operation. It is recommended to use an RC filter at the TRK pin to slow down the slew rate of the command signal at the TRK pin, especially when a step input is applied. When a trapezoidal or sinusoidal input is applied, it is recommended to limit the slew rate or the frequency of the command signal. Bypass mode, OVP and PGOOD functions are based on the TRK pin voltage, see Section 7.4.1.4, Section 7.3.8, Section 7.3.9 respectively.

GUID-55DD1F5D-9A6E-4236-8F5B-53B058671526-low.gif Figure 7-6 TRK Control (a) using VREF (b) by External Step Input